| HiSIM2: Advanced MOSFET model valid for RF circuit simulation M Miura-Mattausch, N Sadachika, D Navarro, G Suzuki, Y Takeda, ... IEEE Transactions on Electron Devices 53 (9), 1994-2007, 2006 | 123 | 2006 |
| A comparison of numerical solutions of the Boltzmann transport equation for high-energy electron transport silicon A Abramo, L Baudry, R Brunetti, R Castagne, M Charef, F Dessenne, ... IEEE Transactions on Electron Devices 41 (9), 1646-1654, 1994 | 90 | 1994 |
| The second-generation of HiSIM_HV compact models for high-voltage MOSFETs HJ Mattausch, M Miyake, T Iizuka, H Kikuchihara, M Miura-Mattausch IEEE transactions on electron devices 60 (2), 653-661, 2012 | 62 | 2012 |
| Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation C Ma, HJ Mattausch, M Miyake, T Iizuka, M Miura-Mattausch, ... 2013 IEEE International Reliability Physics Symposium (IRPS), 2A. 3.1-2A. 3.6, 2013 | 37 | 2013 |
| Advanced short-channel-effect modeling with applicability to device optimization—Potentials and scaling FÁ Herrera, Y Hirano, M Miura-Mattausch, T Iizuka, H Kikuchihara, ... IEEE Transactions on Electron Devices 66 (9), 3726-3733, 2019 | 26 | 2019 |
| Carrier transport simulator for silicon based on carrier distribution function evolutions T Iizuka, M Fukuma Solid-state electronics 33 (1), 27-34, 1990 | 19 | 1990 |
| Advanced electron mobility model of MOS inversion layer considering 2D-degenerate electron gas physics M Ishizaka, T Iizuka, S Ohi, M Fukuma, H Mikoshiba International Technical Digest on Electron Devices, 763-766, 1990 | 16 | 1990 |
| Characteristic length of hot-electron transport in silicon metal–oxide–semiconductor field-effect transistors T Sakamoto, H Kawaura, T Baba, T Iizuka Applied Physics Letters 76 (18), 2618-2620, 2000 | 15 | 2000 |
| MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime Y Takeda, D Navarro, S Chiba, M Miura-Mattausch, HJ Mattausch, ... Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 …, 2005 | 13 | 2005 |
| Modeling of short-channel effect on multi-gate MOSFETs for circuit simulation FÁ Herrera, M Miura-Mattausch, T Iizuka, H Kikuchihara, Y Hirano, ... 2020 International Symposium on Devices, Circuits and Systems (ISDCS), 1-4, 2020 | 11 | 2020 |
| Modeling of carrier transport dynamics at GHz-frequencies for RF circuit-simulation D Navarro, N Nakayama, K Machida, Y Takeda, S Chiba, H Ueno, ... Simulation of Semiconductor Processes and Devices 2004, 259-262, 2004 | 9 | 2004 |
| Ultra-high-performance 0.13-/spl mu/m embedded DRAM technology using TiN/HfO2/TiN/W capacitor and body-slightly-tied SOI Y Aoki, T Ueda, H Shirai, T Sakoh, T Kitamura, S Arai, M Sakao, K Inoue, ... Digest. International Electron Devices Meeting,, 831-834, 2002 | 9 | 2002 |
| Direct observation of hot-electron energy distribution in silicon metal–oxide–semiconductor field-effect transistors T Sakamoto, H Kawaura, T Baba, T Iizuka Applied physics letters 75 (8), 1113-1115, 1999 | 9 | 1999 |
| Simulation-based power-loss optimization of general-purpose high-voltage SiC MOSFET circuit under high-frequency operation A Kar, M Miura-Mattausch, M Sengupta, D Navaroo, H Kikuchihara, ... IEEE Access 9, 23786-23794, 2021 | 8 | 2021 |
| Modeling of NBTI stress induced hole-trapping and interface-state-generation mechanisms under a wide range of bias conditions C Ma, HJ Mattausch, M Miyake, T IIzuka, K Matsuzawa, S Yamaguchi, ... IEICE transactions on electronics 96 (10), 1339-1347, 2013 | 8 | 2013 |
| Characterization of time dependent carrier trapping in poly-crystalline TFTs and its accurate modeling for circuit simulation Y Oodate, H Tanoue, M Miyake, A Tanaka, Y Shintaku, T Nakahagi, ... Proc. SISPAD, 71-74, 2012 | 8 | 2012 |
| Self-heating parameter extraction of power MOSFETs based on transient drain current measurements and on the 2-cell self-heating model R Koh, T Iizuka 2012 IEEE International Conference on Microelectronic Test Structures, 191-195, 2012 | 8 | 2012 |
| Advanced compact MOSFET model HiSIM2 based on surface potentials with a minimum number of approximation M Miura-Mattausch NSTI-Nanotechnology 3, 2006 | 8 | 2006 |
| Leading-edge thin-layer MOSFET potential modeling toward short-channel effect suppression and device optimization FÁ Herrera, Y Hirano, T Iizuka, M Miura-Mattausch, H Kikuchihara, ... IEEE Journal of the Electron Devices Society 7, 1293-1301, 2019 | 7 | 2019 |
| Semiconductor device evaluation apparatus and semiconductor device evaluation method R Koh, T Iizuka US Patent 8,633,726, 2014 | 7 | 2014 |
