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Stijn Eyerman
Stijn Eyerman
Research Scientist, Intel Belgium
Bestätigte E-Mail-Adresse bei intel.com
Titel
Zitiert von
Zitiert von
Jahr
System-level performance metrics for multiprogram workloads
S Eyerman, L Eeckhout
IEEE micro 28 (3), 42-53, 2008
5412008
An evaluation of high-level mechanistic core models
TE Carlson, W Heirman, S Eyerman, I Hur, L Eeckhout
ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 1-25, 2014
4052014
A performance counter architecture for computing accurate CPI components
S Eyerman, L Eeckhout, T Karkhanis, JE Smith
ACM SIGPLAN Notices 41 (11), 175-184, 2006
2652006
A mechanistic performance model for superscalar out-of-order processors
S Eyerman, L Eeckhout, T Karkhanis, JE Smith
ACM Transactions on Computer Systems (TOCS) 27 (2), 1-37, 2009
2472009
Modeling critical sections in Amdahl's law and its implications for multicore design
S Eyerman, L Eeckhout
Proceedings of the 37th annual international symposium on Computer …, 2010
2012010
Interval simulation: Raising the level of abstraction in architectural simulation
D Genbrugge, S Eyerman, L Eeckhout
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
1942010
Fine-grained DVFS using on-chip regulators
S Eyerman, L Eeckhout
ACM Transactions on Architecture and Code Optimization (TACO) 8 (1), 1-24, 2011
1692011
A counter architecture for online DVFS profitability estimation
S Eyerman, L Eeckhout
IEEE Transactions on Computers 59 (11), 1576-1583, 2010
107*2010
Probabilistic job symbiosis modeling for SMT processor scheduling
S Eyerman, L Eeckhout
ACM SIGARCH Computer Architecture News 38 (1), 91-102, 2010
1002010
Criticality stacks: Identifying critical threads in parallel programs using synchronization behavior
K Du Bois, S Eyerman, JB Sartor, L Eeckhout
Proceedings of the 40th annual international symposium on computer …, 2013
992013
Per-thread cycle accounting in SMT processors
S Eyerman, L Eeckhout
ACM Sigplan Notices 44 (3), 133-144, 2009
942009
A memory-level parallelism aware fetch policy for SMT processors
S Everman, L Eeckhout
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
902007
Characterizing the branch misprediction penalty
S Eyerman, JE Smith, L Eeckhout
2006 IEEE International Symposium on Performance Analysis of Systems and …, 2006
832006
Efficient design space exploration of high performance embedded out-of-order processors
S Eyerman, L Eeckhout, K De Bosschere
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
802006
Speedup Stacks: Identifying Scaling Bottlenecks in Multi-Threaded Applications
S Eyerman, K Du Bois, L Eeckhout
ISPASS 2012, 2012
782012
Bottle graphs: Visualizing scalability bottlenecks in multi-threaded applications
K Du Bois, JB Sartor, S Eyerman, L Eeckhout
ACM SIGPLAN Notices 48 (10), 355-372, 2013
642013
Analytical processor performance and power modeling using micro-architecture independent characteristics
S Van den Steen, S Eyerman, S De Pestel, M Mechri, TE Carlson, ...
IEEE Transactions on Computers 65 (12), 3537-3551, 2016
632016
Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware
S Eyerman, K Hoste, L Eeckhout
(IEEE ISPASS) IEEE International Symposium on Performance Analysis of …, 2011
632011
Restating the case for weighted-ipc metrics to evaluate multiprogram workload performance
S Eyerman, L Eeckhout
IEEE Computer Architecture Letters 13 (2), 93-96, 2013
572013
A first-order mechanistic model for architectural vulnerability factor
AA Nair, S Eyerman, L Eeckhout, LK John
ACM SIGARCH Computer Architecture News 40 (3), 273-284, 2012
542012
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