| 14.3 A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy … J Yue, Z Yuan, X Feng, Y He, Z Zhang, X Si, R Liu, MF Chang, X Li, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2020 | 148 | 2020 |
| 15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating J Yue, X Feng, Y He, Y Huang, Y Wang, Z Yuan, M Zhan, J Liu, JW Su, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 238-240, 2021 | 143 | 2021 |
| STICKER: An energy-efficient multi-sparsity compatible accelerator for convolutional neural networks in 65-nm CMOS Z Yuan, Y Liu, J Yue, Y Yang, J Wang, X Feng, J Zhao, X Li, H Yang IEEE Journal of Solid-State Circuits 55 (2), 465-477, 2019 | 84 | 2019 |
| Progressive dnn compression: A key to achieve ultra-high weight pruning and quantization rates using admm S Ye, X Feng, T Zhang, X Ma, S Lin, Z Li, K Xu, W Wen, S Liu, J Tang, ... arXiv preprint arXiv:1903.09769, 2019 | 62 | 2019 |
| STICKER-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse J Yue, Y Liu, Z Yuan, X Feng, Y He, W Sun, Z Zhang, X Si, R Liu, Z Wang, ... IEEE Journal of Solid-State Circuits 57 (8), 2560-2573, 2022 | 47 | 2022 |
| Structadmm: Achieving ultrahigh efficiency in structured pruning for dnns T Zhang, S Ye, X Feng, X Ma, K Zhang, Z Li, J Tang, S Liu, X Lin, Y Liu, ... IEEE transactions on neural networks and learning systems 33 (5), 2259-2273, 2021 | 44 | 2021 |
| 14.2 A 65nm 24.7 µJ/Frame 12.3 mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width … Z Yuan, Y Yang, J Yue, R Liu, X Feng, Z Lin, X Wu, X Li, H Yang, Y Liu 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 232-234, 2020 | 37 | 2020 |
| Seformer: Structure embedding transformer for 3d object detection X Feng, H Du, H Fan, Y Duan, Y Liu Proceedings of the AAAI Conference on Artificial Intelligence 37 (1), 632-640, 2023 | 19 | 2023 |
| An RRAM-based digital computing-in-memory macro with dynamic voltage sense amplifier and sparse-aware approximate adder tree Y He, J Yue, X Feng, Y Huang, H Jia, J Wang, L Zhang, W Sun, H Yang, ... IEEE Transactions on Circuits and Systems II: Express Briefs 70 (2), 416-420, 2022 | 18 | 2022 |
| A 28nm 2D/3D unified sparse convolution accelerator with block-wise neighbor searcher for large-scaled voxel-based point cloud network W Sun, X Feng, C Tang, S Fan, Y Yang, J Yue, H Yang, Y Liu 2023 IEEE International Solid-State Circuits Conference (ISSCC), 328-330, 2023 | 15 | 2023 |
| PATH: Performance-aware task scheduling for energy-harvesting nonvolatile processors J Li, Y Liu, H Li, Z Yuan, C Fu, J Yue, X Feng, CJ Xue, J Hu, H Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018 | 15 | 2018 |
| A sparse-adaptive CNN processor with area/performance balanced N-way set-associate PE arrays assisted by a collision-aware scheduler Z Yuan, J Wang, Y Yang, J Yue, Z Wang, X Feng, Y Wang, X Li, H Yang, ... 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 61-64, 2019 | 14 | 2019 |
| An energy-efficient computing-in-memory NN processor with set-associate blockwise sparsity and ping-pong weight update J Yue, Y Liu, X Feng, Y He, J Wang, Z Yuan, M Zhan, J Liu, JW Su, ... IEEE Journal of Solid-State Circuits 59 (5), 1612-1627, 2023 | 8 | 2023 |
| A 65-nm energy-efficient interframe data reuse neural network accelerator for video applications Y Yang, Y Liu, Z Yuan, W Sun, R Liu, J Wang, J Yue, X Feng, Z Yuan, X Li, ... IEEE Journal of Solid-State Circuits 57 (8), 2574-2585, 2021 | 6 | 2021 |
| Admp: An adversarial double masks based pruning framework for unsupervised cross-domain compression X Feng, Z Yuan, G Wang, Y Liu arXiv preprint arXiv:2006.04127, 2020 | 6 | 2020 |
| Accelerating CNN-RNN based machine health monitoring on FPGA X Feng, J Yue, Q Guo, H Yang, Y Liu 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 6 | 2019 |
| GAAS: An efficient group associated architecture and scheduler module for sparse CNN accelerators J Wang, Z Yuan, R Liu, X Feng, L Du, H Yang, Y Liu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 4 | 2020 |
| A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture Z Wang, J Yue, C He, Z Dai, F Xiang, Z Cong, Y He, X Feng, Y Liu 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 3 | 2023 |
| A 28-nm energy-efficient sparse neural network processor for point cloud applications using block-wise online neighbor searching X Feng, W Sun, C Tang, X Lin, J Yue, H Yang, Y Liu IEEE Journal of Solid-State Circuits, 2024 | 2 | 2024 |
| A 28nm 1.2 GHz 5.27 TOPS/W Scalable Vision/Point Cloud Deep Fusion Processor with CAM-based Universal Mapping Unit for BEVFusion Applications X Feng, W Sun, X Lin, S Fan, H Yang, Y Liu 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024 | 1 | 2024 |
