| Verifying software network functions with no verification expertise A Zaostrovnykh, S Pirelli, R Iyer, M Rizzo, L Pedrosa, K Argyraki, ... Proceedings of the 27th ACM Symposium on Operating Systems Principles, 275-290, 2019 | 62 | 2019 |
| Performance contracts for software network functions R Iyer, L Pedrosa, A Zaostrovnykh, S Pirelli, K Argyraki, G Candea 16th USENIX Symposium on Networked Systems Design and Implementation (NSDI …, 2019 | 61 | 2019 |
| Automated synthesis of adversarial workloads for network functions L Pedrosa, R Iyer, A Zaostrovnykh, J Fietz, K Argyraki Proceedings of the 2018 Conference of the ACM Special Interest Group on Data …, 2018 | 55 | 2018 |
| Bypassing the load balancer without regrets M Kogias, R Iyer, E Bugnion Proceedings of the 11th ACM Symposium on Cloud Computing, 193-207, 2020 | 29 | 2020 |
| Performance interfaces for network functions R Iyer, K Argyraki, G Candea 19th USENIX Symposium on Networked Systems Design and Implementation (NSDI …, 2022 | 25 | 2022 |
| Achieving microsecond-scale tail latency efficiently with approximate optimal scheduling R Iyer, M Unal, M Kogias, G Candea Proceedings of the 29th Symposium on Operating Systems Principles, 466-481, 2023 | 12 | 2023 |
| Performance modelling and dynamic scheduling on heterogeneous-ISA multi-core architectures NK Boran, DK Yadav, R Iyer VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 7 | 2019 |
| The case for performance interfaces for hardware accelerators R Iyer, J Ma, K Argyraki, G Candea, S Ratnasamy Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 38-45, 2023 | 6 | 2023 |
| Classification based scheduling in Heterogeneous ISA Architectures NK Boran, DK Yadav, R Iyer 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-6, 2020 | 5 | 2020 |
| Fast, Flexible, and Practical Kernel Extensions KK Dwivedi, R Iyer, S Kashyap Proceedings of the ACM SIGOPS 30th Symposium on Operating Systems Principles …, 2024 | 4 | 2024 |
| Automatically Reasoning About How Systems Code Uses the CPU Cache R Iyer, K Argyraki, G Candea 18th USENIX Symposium on Operating Systems Design and Implementation (OSDI …, 2024 | 3 | 2024 |
| Performance interfaces for hardware accelerators J Ma, R Iyer, S Kashani, M Emami, T Bourgeat, G Candea 18th USENIX Symposium on Operating Systems Design and Implementation (OSDI …, 2024 | 3 | 2024 |
| If Layering is useful, why not Sublayering? R Singha, R Iyer, C Liu, C Terrill, T Millstein, S Shenker, G Varghese Proceedings of the 23rd ACM Workshop on Hot Topics in Networks, 142-149, 2024 | 1 | 2024 |
| Revisiting Cache Freshness for Emerging Real-Time Applications Z Mao, R Iyer, S Shenker, I Stoica Proceedings of the 23rd ACM Workshop on Hot Topics in Networks, 335-342, 2024 | 1 | 2024 |
| The Case for Validating Inputs in Software-Defined WANs A Krentsel, R Iyer, I Keslassy, S Ratnasamy, A Shaikh, R Shakir Proceedings of the 23rd ACM Workshop on Hot Topics in Networks, 246-254, 2024 | 1 | 2024 |
| Latency Interfaces for Systems Code RR Iyer https://dslab.epfl.ch/pubs/phd-iyer.pdf, 2023 | | 2023 |
George CandeaAssociate Professor of Computer Science, EPFL (Lausanne, Switzerland)Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα epfl.ch
