| Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems H Asghari-Moghaddam, YH Son, JH Ahn, NS Kim 2016 49th annual IEEE/ACM international symposium on Microarchitecture …, 2016 | 188 | 2016 |
| Reducing memory access latency with asymmetric DRAM bank organizations YH Son, O Seongil, Y Ro, JW Lee, JH Ahn Proceedings of the 40th annual international symposium on computer …, 2013 | 171 | 2013 |
| Defect analysis and cost-effective resilience architecture for future DRAM devices S Cha, O Seongil, H Shin, S Hwang, K Park, SJ Jang, JS Choi, GY Jin, ... 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 80 | 2017 |
| CiDRA: A cache-inspired DRAM resilience architecture YH Son, S Lee, O Seongil, S Kwon, NS Kim, JH Ahn 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 60 | 2015 |
| A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme YC Bae, JY Park, SJ Rhee, SB Ko, Y Jeong, KS Noh, Y Son, J Youn, ... 2012 IEEE International Solid-State Circuits Conference, 44-46, 2012 | 48 | 2012 |
| Row-buffer decoupling: A case for low-latency DRAM microarchitecture O Seongil, YH Son, NS Kim, JH Ahn 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014 | 47 | 2014 |
| Understanding ddr4 in pursuit of in-dram ecc S Kwon, YH Son, JH Ahn 2014 International SoC Design Conference (ISOCC), 276-277, 2014 | 33 | 2014 |
| Leveraging power-performance relationship of energy-efficient modern DRAM devices S Lee, H Cho, YH Son, Y Ro, NS Kim, JH Ahn IEEE Access 6, 31387-31398, 2018 | 30 | 2018 |
| Microbank: Architecting through-silicon interposer-based main memory systems YH Son, O Seongil, H Yang, D Jung, JH Ahn, J Kim, J Kim, JW Lee SC'14: Proceedings of the International Conference for High Performance …, 2014 | 27 | 2014 |
| A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM with various high-speed and low-power techniques KS Ha, CK Lee, D Lee, D Moon, HR Hwang, D Park, YH Kim, YH Son, ... IEEE Journal of Solid-State Circuits 55 (1), 157-166, 2019 | 25 | 2019 |
| 23.1 a 7.5 Gb/s/pin LPDDR5 SDRAM with WCK clocking and non-target ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power KS Ha, CK Lee, D Lee, D Moon, JH Jang, HR Hwang, H Chi, J Park, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2019 | 25 | 2019 |
| 22.2 An 8.5 Gb/s/pin 12Gb-LPDDR5 SDRAM with a hybrid-bank architecture using skew-tolerant, low-power and speed-boosting techniques in a 2nd generation 10nm DRAM process HJ Chi, CK Lee, J Park, JS Heo, J Jung, D Lee, DH Kim, D Park, K Kim, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 382-384, 2020 | 21 | 2020 |
| Scalable high-radix router microarchitecture using a network switch organization JH Ahn, YH Son, J Kim ACM Transactions on Architecture and Code Optimization (TACO) 10 (3), 1-25, 2013 | 15 | 2013 |
| SALAD: Achieving symmetric access latency with asymmetric DRAM architecture YH Son, H Cho, Y Ro, JW Lee, JH Ahn IEEE Computer Architecture Letters 16 (1), 76-79, 2016 | 8 | 2016 |
| SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures Y Ro, H Cho, E Lee, D Jung, YH Son, JH Ahn, JW Lee 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 7 | 2017 |
| Greendimm: Os-assisted dram power management for dram with a sub-array granularity power-down state S Lee, KD Kang, H Lee, H Park, Y Son, NS Kim, D Kim MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 5 | 2021 |
| Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM CK Lee, J Lee, KH Kim, JS Heo, GH Cha, JH Baek, DS Moon, YJ Eom, ... 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 153-156, 2017 | 5 | 2017 |
| Understanding power-performance relationship of energy-efficient modern DRAM devices S Lee, Y Ro, YH Son, H Cho, NS Kim, JH Ahn 2017 IEEE International Symposium on Workload Characterization (IISWC), 110-111, 2017 | 5 | 2017 |
| Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os DW Chang, YH Son, JH Ahn, H Kim, M Ahn, MJ Schulte, NS Kim 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 747-754, 2013 | 5 | 2013 |
| Output driver, and semiconductor memory device and memory system having the same YH Son, JH Choi, SH Hyun US Patent 10,566,968, 2020 | 4 | 2020 |
