| MIRA: A multi-layered on-chip interconnect router architecture D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das ACM SIGARCH Computer Architecture News 36 (3), 251-261, 2008 | 305 | 2008 |
| Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs R Das, S Eachempati, AK Mishra, V Narayanan, CR Das 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 255 | 2009 |
| A case for dynamic frequency tuning in on-chip networks AK Mishra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, CR Das Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 150 | 2009 |
| Expression of Concern: Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures S Eachempati, A Nieuwoudt, A Gayasen, N Vijaykrishnan, Y Massoud 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 81 | 2007 |
| RAFT: A router architecture with frequency tuning for on-chip networks AK Mishra, A Yanamandra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, ... Journal of Parallel and Distributed Computing 71 (5), 625-640, 2011 | 38 | 2011 |
| Automated mapping for reconfigurable single-electron transistor arrays YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan Proceedings of the 48th Design Automation Conference, 878-883, 2011 | 30 | 2011 |
| Reconfigurable BDD based quantum circuits S Eachempati, V Saripalli, N Vijaykrishnan, S Datta 2008 IEEE International Symposium on Nanoscale Architectures, 61-67, 2008 | 28 | 2008 |
| Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines R Manimegalai, ES Soumya, V Muralidharan, B Ravindran, V Kamakoti VLSI Design, 2005. 18th International Conference on, 451-456, 2005 | 24 | 2005 |
| Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect S Eachempati, N Vijaykrishnan, A Nieuwoudt, Y Massoud IET circuits, devices & systems 3 (2), 64-75, 2009 | 23 | 2009 |
| A synthesis algorithm for reconfigurable single-electron transistor arrays YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (1), 1-20, 2013 | 21 | 2013 |
| Optimizing power and performance for reliable on-chip networks A Yanamandra, S Eachempati, N Soundararajan, V Narayanan, MJ Irwin, ... 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 431-436, 2010 | 20 | 2010 |
| Design and evaluation of hierarchical on-chip network topologies for next generation CMPs R Das, S Eachempati, AK Mishra, N Vijaykrishnan, CR Das HPCA-15 2, 2009 | 17 | 2009 |
| Leveraging emerging technology through architectural exploration for the routing fabric of future FPGAs S Eachempati, A Gayasen, N Vijaykrishnan, MJ Irwin Nanoelectronic Circuit Design, 189-213, 2011 | 4 | 2011 |
| Reetuparna Das, Asit K Mishra, Yuan Xie, Narayanan Vijaykrishnan, and Chita R Das. 2008. MIRA: a multi-layered on-chip interconnect router architecture D Park, S Eachempati ACM SIGARCH Computer Architecture News 36, 251-261, 0 | 4 | |
| Impact of process variations on carbon nanotube bundle interconnect for future FPGA architectures S Eachempati, N Vijaykrishnan, A Nieuwoudt, Y Massoud IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 516-517, 2007 | 3 | 2007 |
| Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network Y Xie, S Eachempati, A Yanamandra, V Narayanan, MJ Irwin 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 51-56, 2009 | 2 | 2009 |
| HeTERO: Hybrid Topology Exploration for RF-Based On-Chip Networks S Eachempati, R Das, V Narayanan, Y Xie, S Datta, CR Das Communication Architectures for Systems-on-Chip, 231-278, 2018 | | 2018 |
| HeTERO: Hybrid Topology Exploration for RF-Based On-Chip Networks S Eachempati, R Das, V Narayanan, Y Xie, S Datta, CR Das Communication Architectures for Systems-on-Chip, 231-278, 2018 | | 2018 |
| Three-dimensional On-chip Interconnect Architectures S Eachempati, D Park, R Das, AK Mishra, V Narayanan, Y Xie, C Das Designing Network On-Chip Architectures in the Nanoscale Era, 353-381, 2010 | | 2010 |
| Non-silicon logic elements on silicon for extreme voltage scaling S Datta, A Ali, S Mookerjea, V Saripalli, L Liu, S Eachempati, T Mayer, ... 2010 Silicon Nanoelectronics Workshop, 1-2, 2010 | | 2010 |
Vijaykrishnan NarayananRobert Noll Chair Professor at The Pennsylvania State UniversityΗ διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα cse.psu.edu
