| An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications S Khan, AP Shah, N Gupta, SS Chouhan, JG Pandey, SK Vishvakarma Microelectronics journal 92, 104605, 2019 | 30 | 2019 |
| A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher JG Pandey, SM IEEE, T Goel, A Karmakar in Proceeding: 31st International Conference on VLSI Design and 2018 17th …, 2018 | 30 | 2018 |
| Hardware architectures for PRESENT block cipher and their FPGA implementations JG Pandey, T Goel, A Karmakar IET Circuits, Devices & Systems 13 (7), 958-969, 2019 | 28 | 2019 |
| An architecture for 32-bit energy-efficient wallace tree carry save adder JG Pandey, G Dhiman 2017 2nd International Conference on Telecommunication and Networks (TEL-NET …, 2017 | 25 | 2017 |
| Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications S Khan, AP Shah, SS Chouhan, S Rani, N Gupta, JG Pandey, ... Analog Integrated Circuits and Signal Processing 103 (3), 477-492, 2020 | 23 | 2020 |
| A novel architecture for FPGA implementation of Otsu's global automatic image thresholding algorithm JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 23 | 2014 |
| GIFT Cipher Usage in Image Data Security: Hardware Implementations, Performance and Statistical Analyses A Jangir, JG Pandey Journal of Real-Time Image Processing, 2021 | 19 | 2021 |
| A symmetric D flip-flop based PUF with improved uniqueness S Khan, AP Shah, SS Chouhan, N Gupta, JG Pandey, SK Vishvakarma Microelectronics Reliability 106, 113595, 2020 | 19 | 2020 |
| An efficient VLSI architecture for PRESENT block cipher and its FPGA implementation JG Pandey, T Goel, A Karmakar VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017 | 18 | 2017 |
| Logic locking for IP security: a comprehensive analysis on challenges, techniques, and trends J Gandhi, D Shekhawat, M Santosh, JG Pandey Computers & Security 129, 103196, 2023 | 16 | 2023 |
| An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation JG Pandey, SM IEEE, A Gurawa, H Nehra, A Karmakar 2nd IEEE Int’l Conf. on VLSI Systems, Architecture, Technology and …, 2016 | 16 | 2016 |
| Platform-Based Extensible Hardware-Software Video Streaming Module for a Smart Camera System JG Pandey, S Purushottam, A Karmakar, C Shekhar International Journal of Modeling and Optimization 2 (4), 482-487, 2012 | 16 | 2012 |
| An FPGA-based fixed-point architecture for binary logarithmic computation JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan 2013 IEEE Second International Conference on Image Information Processing …, 2013 | 14 | 2013 |
| An RNS Implementation of the Elliptic Curve Cryptography for IoT Security JG Pandey, C Mitharwal, A Karmakar IEEE International Conference on Trust, Privacy and Security in Intelligent …, 2019 | 12 | 2019 |
| A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA JG Pandey, A Laddha, SD Samaddar 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar …, 2020 | 11 | 2020 |
| An FPGA-based architecture for local similarity measure for image/video processing applications JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan 2015 28th international conference on VLSI design, 339-344, 2015 | 11 | 2015 |
| Implementation of an Improved Connected Component Labeling Algorithm using FPGA-based Platform JG Pandey, A Karmakar, AK Mishra, C Shekhar, S Gurunarayanan Signal Processing and Communications (SPCOM), 2014 International Conference …, 2014 | 11 | 2014 |
| Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform JG Pandey, A Karmakar International Journal of Electronics 106 (3), 455-476, 2019 | 10 | 2019 |
| Platform-Based Design Approach for Embedded Vision Applications JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan Journal of Image and Graphics 1 (1), 1-6, 2013 | 10 | 2013 |
| An embedded FPGA-SoC framework and its usage in moving object tracking application JG Pandey Design Automation for Embedded Systems, 2021 | 7 | 2021 |
Diksha ShekhawatPh.D. Research Scholar, AcSIR, CSIR-CEERI, PilaniΗ διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα ceeri.res.in
