| EIE: Efficient inference engine on compressed deep neural network S Han, X Liu, H Mao, J Pu, A Pedram, MA Horowitz, WJ Dally ACM SIGARCH Computer Architecture News 44 (3), 243-254, 2016 | 3352 | 2016 |
| Plasticine: A Reconfigurable Architecture For Parallel Patterns R Prabhakar, Y Zhang, D Koeplinger, M Feldman, T Zhao, S Hadjis, ... 44th International Symposium on Computer Architecture (ISCA 2017), 2017 | 350 | 2017 |
| Spatial: A language and compiler for application accelerators D Koeplinger, M Feldman, R Prabhakar, Y Zhang, S Hadjis, R Fiszel, ... Proceedings of the 39th ACM SIGPLAN Conference on Programming Language …, 2018 | 275 | 2018 |
| Dark memory and accelerator-rich system optimization in the dark silicon era A Pedram, S Richardson, S Galal, S Kvatinsky, M Horowitz IEEE Design & Test 34 (2), 39-50, 2017 | 169 | 2017 |
| A systematic approach to blocking convolutional neural networks X Yang, J Pu, BB Rister, N Bhagdikar, S Richardson, S Kvatinsky, ... arXiv preprint arXiv:1606.04209, 2016 | 80 | 2016 |
| Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures A Pedram, A Gerstlauer, RA van de Geijn IEEE Transactions on Computers 61 (12), 1724 - 1736, 2012 | 76 | 2012 |
| Deep compression and EIE: Efficient inference engine on compressed deep neural network. S Han, X Liu, H Mao, J Pu, A Pedram, M Horowitz, B Dally Hot Chips Symposium, 1-6, 2016 | 62 | 2016 |
| Evaluating Programmable Architectures for Imaging and Vision Applications A Vasilyev, N Bhagdikar, A Pedram, S Richardson, S Kvatinsky, ... IEEE/ACM International Symposium on Microarchitecture, 2016 | 52 | 2016 |
| Local linear model tree (LOLIMOT) reconfigurable parallel hardware A Pedram, MR Jamali, T Pedram, SM Fakhraie, C Lucas International Journal of Applied Science, Engineering and Technology 1, 1, 2006 | 40 | 2006 |
| A high-performance, low-power linear algebra core A Pedram, A Gerstlauer, RA Van De Geijn Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE …, 2011 | 35 | 2011 |
| CATERPILLAR: Coarse Grain Reconfigurable Architecture for Accelerating the Training of Deep Neural Networks Y Li, A Pedram The 28th Annual IEEE International Conference on Application-specific …, 2017 | 30 | 2017 |
| Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access H Ha, A Pedram, S Richardson, S Kvatinsky, M Horowitz IEEE/ACM International Symposium on Microarchitecture, 2016 | 27 | 2016 |
| Modeling cache effects at the transaction level A Pedram, D Craven, A Gerstlauer Analysis, Architectures and Modelling of Embedded Systems: Third IFIP TC 10 …, 2009 | 25 | 2009 |
| Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator A Pedram, A Gerstlauer, RA van de Geijn | 24 | 2014 |
| Plasticine: a reconfigurable accelerator for parallel patterns R Prabhakar, Y Zhang, D Koeplinger, M Feldman, T Zhao, S Hadjis, ... IEEE Micro 38 (3), 20-31, 2018 | 22 | 2018 |
| A Linear Algebra Core Design For Efficient Level-3 BLAS A Pedram, SZ Gilani, NS Kim, R van de Geijn, M Schulte, A Gerstlauer Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE …, 2012 | 22 | 2012 |
| A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores A Pedram, JD McCalpin, A Gerstlauer Journal of Signal Processing Systems, 2014 | 20 | 2014 |
| Griffin: Rethinking Sparse Optimization for Deep Learning Architectures JH Shin, A Shafiee, A Pedram, H Abdel-Aziz, L Li, J Hassoun HPCA 2022, 2021 | 19* | 2021 |
| Distributing congestions in NOCs through a dynamic routing algorithm based on input and output selections M Daneshtalab, A Pedram, MH Neishaburi, M Riazati, A Afzali-Kusha, ... VLSI Design, 2007. Held jointly with 6th International Conference on …, 2007 | 17 | 2007 |
| Campfire: Compressible, Regularization-Free, Structured Sparse Training for Hardware Accelerators N Gamboa, K Kudrolli, A Dhoot, A Pedram arXiv preprints, 2020 | 16 | 2020 |
