| Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications MR Tripathy, AK Singh, A Samad, S Chander, K Baral, PK Singh, S Jit IEEE Transactions on Electron Devices 67 (3), 1285-1292, 2020 | 132 | 2020 |
| 2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure S Kumar, K Singh, S Chander, E Goel, PK Singh, K Baral, B Singh, S Jit IEEE Transactions on Electron Devices 65 (1), 331-338, 2017 | 69 | 2017 |
| Temperature analysis of Ge/Si heterojunction SOI-tunnel FET S Chander, SK Sinha, S Kumar, PK Singh, K Baral, K Singh, S Jit Superlattices and Microstructures 110, 162-170, 2017 | 62 | 2017 |
| Heterojunction fully depleted SOI-TFET with oxide/source overlap S Chander, B Bhowmick, S Baishya Superlattices and Microstructures 86, 43-50, 2015 | 57 | 2015 |
| Comprehensive review on electrical noise analysis of TFET structures S Chander, SK Sinha, R Chaudhary Superlattices and Microstructures 161, 107101, 2022 | 55 | 2022 |
| A two-dimensional gate threshold voltage model for a heterojunction SOI-tunnel FET with oxide/source overlap S Chander, S Baishya IEEE Electron device letters 36 (7), 714-716, 2015 | 47 | 2015 |
| Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs S Chander, S Baishya, SK Sinha, S Kumar, PK Singh, K Baral, ... Superlattices and Microstructures 131, 30-39, 2019 | 41 | 2019 |
| Simulation study and comparative analysis of some TFET structures with a novel partial-ground-plane (PGP) based TFET on SELBOX structure AK Singh, MR Tripathy, S Chander, K Baral, PK Singh, S Jit Silicon 12, 2345-2354, 2020 | 35 | 2020 |
| Reliability models with priority for operation and repair with arrival time of server S Chander Pure and Applied Mathematika Sciences 61 (1-2), 9-22, 2005 | 35 | 2005 |
| Ge-source based L-shaped tunnel field effect transistor for low power switching application S Chander, SK Sinha, R Chaudhary, A Singh Silicon, 1-14, 2021 | 33 | 2021 |
| Reliability and economic analysis of 2-out-of-3 redundant system with priority to repair S Chander, RK Bhardwaj African J. of Maths and comp. sci 2 (11), 230-236, 2009 | 33 | 2009 |
| Performance analysis of heterojunction tunnel FET device with variable temperature IA Pindoo, SK Sinha, S Chander Applied Physics A 127, 1-10, 2021 | 31 | 2021 |
| Profit analysis of single-unit reliability models with repair at different failure modes S Chander, RK Bansal Proc. INCRESE IIT Kharagpur, India, 577-587, 2005 | 29 | 2005 |
| Improvement of electrical characteristics of SiGe source based tunnel FET device IA Pindoo, SK Sinha, S Chander Silicon 13 (9), 3209-3215, 2021 | 28 | 2021 |
| Behaviour of β-Cyfluthrin and Imidacloprid in Mustard Crop: Alternative Insecticide for Aphid Control. M Gopal, I Mukherjee, S Chander Bulletin of Environmental Contamination & Toxicology 68 (3), 2002 | 25 | 2002 |
| Effect of noise components on L-shaped and T-shaped heterojunction tunnel field effect transistors S Chander, SK Sinha, R Chaudhary, R Goswami Semiconductor Science and Technology 37 (7), 075011, 2022 | 24 | 2022 |
| Stochastic analysis of non-identical units reliability models with priority and different modes of failure MS Kadyan, S Chander, AS Grewal Decision and Mathematical Sciences 9 (1-3), 59-82, 2004 | 23 | 2004 |
| Investigation of DC performance of Ge-source pocket silicon-on-insulator tunnel field effect transistor in nano regime SK Sinha, S Chander International Journal of Nanoparticles 13 (1), 13-20, 2021 | 21 | 2021 |
| Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis PK Singh, K Baral, S Kumar, S Chander, MR Tripathy, AK Singh, S Jit Applied Physics A 126, 1-11, 2020 | 19 | 2020 |
| Two-dimensional model of a heterojunction silicon-on-insulator tunnel field effect transistor S Chander, S Baishya Superlattices and Microstructures 90, 176-183, 2016 | 19 | 2016 |