| Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor A Chattopadhyay, A Mallik IEEE Transactions on Electron Devices 58 (3), 677-683, 2011 | 175 | 2011 |
| Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications A Mallik, A Chattopadhyay IEEE Transactions on Electron Devices 59 (4), 888-894, 2012 | 138 | 2012 |
| Drain-dependence of tunnel field-effect transistor characteristics: The role of the channel A Mallik, A Chattopadhyay IEEE transactions on electron devices 58 (12), 4250-4257, 2011 | 91 | 2011 |
| Comparison of random dopant and gate-metal workfunction variability between junctionless and conventional FinFETs SM Nawaz, S Dutta, A Chattopadhyay, A Mallik IEEE electron device letters 35 (6), 663-665, 2014 | 65 | 2014 |
| Impact of a pocket doping on the device performance of a Schottky tunneling field-effect transistor S Guin, A Chattopadhyay, A Karmakar, A Mallik IEEE transactions on electron devices 61 (7), 2515-2522, 2014 | 64 | 2014 |
| Impact of a spacer–drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling A Mallik, A Chattopadhyay, S Guin, A Karmakar IEEE transactions on electron devices 60 (3), 935-943, 2013 | 59 | 2013 |
| Optimization of hetero-gate-dielectric tunnel FET for label-free detection and identification of biomolecules S Ghosh, A Chattopadhyay, S Tewari IEEE transactions on Electron Devices 67 (5), 2157-2164, 2020 | 44 | 2020 |
| The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High- Gate Dielectric A Mallik, A Chattopadhyay IEEE transactions on electron devices 59 (2), 277-282, 2011 | 41 | 2011 |
| Temperature dependence of analog performance, linearity, and harmonic distortion for a ge-source tunnel FET E Datta, A Chattopadhyay, A Mallik, Y Omura IEEE Transactions on Electron Devices 67 (3), 810-815, 2020 | 39 | 2020 |
| On the implementation of a copyright protection scheme using digital image watermarking S Sinha Roy, A Basu, A Chattopadhyay Multimedia Tools and Applications 79 (19), 13125-13138, 2020 | 31 | 2020 |
| Relative study of analog performance, linearity, and harmonic distortion between junctionless and conventional SOI FinFETs at elevated temperatures E Datta, A Chattopadhyay, A Mallik Journal of Electronic Materials 49, 3309-3316, 2020 | 28 | 2020 |
| Dual-metal double-gate with low-k/high-k oxide stack junctionless MOSFET for a wide range of protein detection: a fully electrostatic based numerical approach A Chattopadhyay, S Tewari, PS Gupta Silicon 13, 441-450, 2021 | 27 | 2021 |
| Implementation of a spatial domain salient region based digital image watermarking scheme A Basu, SS Roy, A Chattopadhyay 2016 Second International Conference on Research in Computational …, 2016 | 16 | 2016 |
| Intelligent copyright protection for images SS Roy, A Basu, A Chattopadhyay Chapman and Hall/CRC, 2019 | 15 | 2019 |
| Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor A Chattopadhyay, A Mallik, Y Omura Superlattices and Microstructures 82, 415-429, 2015 | 15 | 2015 |
| Gate-on-germanium source tunnel field-effect transistor enabling sub-0.5-V operation A Mallik, A Chattopadhyay, Y Omura Japanese Journal of Applied Physics 53 (10), 104201, 2014 | 10 | 2014 |
| Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study S Das, A Chattopadhyay, S Tewari IEEE Transactions on Electron Devices 69 (11), 6430-6437, 2022 | 8 | 2022 |
| Implementation of image copyright protection tool using hardware-software co-simulation S Sinha Roy, A Basu, A Chattopadhyay, TS Das Multimedia Tools and Applications 80 (3), 4263-4277, 2021 | 8 | 2021 |
| Asymmetric-elevated-source-drain TFET: a fairly scalable and reliable device architecture for sub-400-mV low-stand-by-power digital applications S Das, A Chattopadhyay, S Tewari IETE Technical Review 39 (2), 316-327, 2022 | 7 | 2022 |
| A comparison of analog performance, linearity, and distortion characteristics between symmetric InGaAs and asymmetric InGaAs/InP MOSFETs E Datta, A Chattopadhyay, A Mallik IEEE Transactions on electron devices 68 (4), 1570-1576, 2021 | 7 | 2021 |
Abhijit MallikUniversity of CalcuttaVerified email at caluniv.ac.in
