Minimum cost fault tolerant adder circuits in reversible logic synthesis SK Mitra, AR Chowdhury 2012 25th International Conference on VLSI Design, 334-339, 2012 | 66 | 2012 |
Efficient approach to design low power reversible logic blocks for Field Programmable Gate Arrays ASM Sayem, SK Mitra Computer Science and Automation Engineering (CSAE), 2011 IEEE International …, 2011 | 18 | 2011 |
On the analysis of Reversible Booth's Multiplier J Sultana, SK Mitra, AR Chowdhury 2015 28th International Conference on VLSI Design, 170-175, 2015 | 16 | 2015 |
An efficient approach for designing and minimizing reversible programmable logic arrays SK Mitra, L Jamal, M Kaneko, HM Hasan Babu Proceedings of the great lakes symposium on VLSI, 215-220, 2012 | 14 | 2012 |
Optimized logarithmic barrel shifter in reversible logic synthesis SK Mitra, AR Chowdhury 2015 28th International Conference on VLSI Design, 441-446, 2015 | 10 | 2015 |
Efficient Approach to design Reversible FaultTolerant Cyclic Redundancy Check Circuit SK Mitra, T Sultana, S Anwar, AR Chowdhury Second International Conference on Signals, Systems & Automation (ICSSA-11 …, 2011 | 1 | 2011 |
Reversible Programmable Logic Arrays SK Mitra, MR Rahman 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | | 2016 |
An efficient approach for designing and minimizing reversible programmable logic arrays M Kaneko, SK Mitra, HMH Babu, L Jamal Proceedings of the great lakes symposium on VLSI, 2012 | | 2012 |
Efficient Design of Check Circuit to detect MultipleCell Errors in Reversible Logic Synthesis SK Mitra, AR Anwar, Shahed, Chowdhury Second International Conference on Signals, Systems & Automation (ICSSA-11 …, 2011 | | 2011 |
Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis SK Mitra, MF Hossain, S Anwar, AR Chowdhury Second International Conference on Signals, Systems & Automation (ICSSA-11 …, 2011 | | 2011 |