| FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ... IEEE Journal of the Electron Devices Society 6, 332-340, 2018 | 227 | 2018 |
| Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes D Nagy, G Espineira, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane IEEE Access 8, 53196-53202, 2020 | 112 | 2020 |
| Quantum-transport study on the impact of channel length and cross sections on variability induced by random discrete dopants in narrow gate-all-around silicon nanowire transistors A Martinez, M Aldegunde, N Seoane, AR Brown, JR Barker, A Asenov IEEE Transactions on Electron Devices 58 (8), 2209-2217, 2011 | 84 | 2011 |
| Current variability in Si nanowire MOSFETs due to random dopants in the source/drain regions: A fully 3-D NEGF simulation study N Seoane, A Martinez, AR Brown, JR Barker, A Asenov IEEE Transactions on electron devices 56 (7), 1388-1395, 2009 | 83 | 2009 |
| Implementation of the density gradient quantum corrections for 3-D simulations of multigate nanoscaled transistors AJ Garcia-Loureiro, N Seoane, M Aldegunde, R Valin, A Asenov, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 80 | 2011 |
| Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques A Asenov, AR Brown, G Roy, B Cheng, C Alexander, C Riddet, U Kovac, ... Journal of computational electronics 8, 349-373, 2009 | 78 | 2009 |
| Variability in Si nanowire MOSFETs due to the combined effect of interface roughness and random dopants: A fully three-dimensional NEGF simulation study A Martinez, N Seoane, AR Brown, JR Barker, A Asenov IEEE Transactions on electron devices 57 (7), 1626-1635, 2010 | 69 | 2010 |
| Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs FinFET N Seoane, G Indalecio, E Comesana, M Aldegunde, AJ Garcia-Loureiro, ... IEEE Transactions on Electron Devices 61 (2), 466-472, 2013 | 63 | 2013 |
| Advanced simulation of statistical variability and reliability in nano CMOS transistors A Asenov, S Roy, RA Brown, G Roy, C Alexander, C Riddet, C Millar, ... 2008 IEEE International Electron Devices Meeting, 1-1, 2008 | 50 | 2008 |
| Benchmarking of scaled InGaAs implant-free nanoMOSFETs K Kalna, N Seoane, AJ Garcia-Loureiro, IG Thayne, A Asenov IEEE transactions on electron devices 55 (9), 2297-2306, 2008 | 49 | 2008 |
| Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs N Seoane, G Indalecio, M Aldegunde, D Nagy, MA Elmessary, ... IEEE Transactions on Electron Devices 63 (3), 1209-1216, 2016 | 48 | 2016 |
| Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations MA Elmessary, D Nagy, M Aldegunde, N Seoane, G Indalecio, J Lindberg, ... Solid-State Electronics 128, 17-24, 2017 | 46 | 2017 |
| Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs N Seoane, JG Fernandez, K Kalna, E Comesana, A Garcia-Loureiro IEEE Electron Device Letters 42 (10), 1416-1419, 2021 | 45 | 2021 |
| 3-D nonequilibrium Green's function simulation of nonperturbative scattering from discrete dopants in the source and drain of a silicon nanowire transistor A Martinez, N Seoane, AR Brown, JR Barker, A Asenov IEEE Transactions on Nanotechnology 8 (5), 603-610, 2009 | 42 | 2009 |
| Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET G Espineira, D Nagy, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane IEEE Electron Device Letters 40 (4), 510-513, 2019 | 38 | 2019 |
| Study of metal-gate work-function variation using Voronoi cells: Comparison of Rayleigh and gamma distributions G Indalecio, AJ Garcia-Loureiro, NS Iglesias, K Kalna IEEE Transactions on Electron Devices 63 (6), 2625-2628, 2016 | 31 | 2016 |
| Metal grain granularity study on a gate-all-around nanowire FET D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ... IEEE Transactions on Electron Devices 64 (12), 5263-5269, 2017 | 30 | 2017 |
| Vertical-tunnel-junction (VTJ) solar cell for ultra-high light concentrations (> 2000 suns) EF Fernández, N Seoane, F Almonacid, AJ García-Loureiro IEEE Electron Device Letters 40 (1), 44-47, 2018 | 29 | 2018 |
| Impact of cross-sectional shape on 10-nm gate length InGaAs FinFET performance and variability N Seoane, G Indalecio, D Nagy, K Kalna, AJ Garcia-Loureiro IEEE Transactions on Electron Devices 65 (2), 456-462, 2018 | 27 | 2018 |
| Reduction of the self-forces in Monte Carlo simulations of semiconductor devices on unstructured meshes M Aldegunde, N Seoane, AJ García-Loureiro, K Kalna Computer Physics Communications 181 (1), 24-34, 2010 | 27 | 2010 |
