| Delay estimates for graphene nanoribbons: A novel measure of fidelity and experiments with global routing trees S Das, S Das, A Majumder, P Dasgupta, DK Das Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 263-268, 2016 | 18 | 2016 |
| A technique to construct global routing trees for graphene nanoribbon (GNR) S Das, DK Das 2017 18th International symposium on quality electronic design (ISQED), 111-118, 2017 | 13 | 2017 |
| Arithmetic algorithms for ternary number system S Das, PS Dasgupta, S Sensarma Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 11 | 2012 |
| Algorithms for ternary number system S Das, JP Sain, P Dasgupta, S Sensarma Procedia Technology 4, 278-285, 2012 | 8 | 2012 |
| A global routing method for graphene nanoribbons based circuits and interconnects S Das, DK Das, S Pandit ACM Journal on Emerging Technologies in Computing Systems (JETC) 16 (3), 1-28, 2020 | 6 | 2020 |
| A rule-based approach for minimizing power dissipation of digital circuits S Das, P Dasgupta, P Fiser, S Ghosh, DK Das 2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016 | 6 | 2016 |
| Steiner tree construction for graphene nanoribbon based circuits in presence of obstacles S Das, DK Das 2018 International Symposium on Devices, Circuits and Systems (ISDCS), 1-6, 2018 | 4 | 2018 |
| Minimization of switching activity of graphene based circuits S Das, P Fiser, S Pandit, DK Das 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 3 | 2021 |
| An angular steiner tree based global routing algorithm for graphene nanoribbon circuit A Sinharay, S Das, P Roy, H Rahaman International Symposium on VLSI Design and Test, 670-681, 2018 | 2 | 2018 |
| A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issues S Das, DK Das, S Pandit Analog Integrated Circuits and Signal Processing 116 (1-2), 49-67, 2023 | 1 | 2023 |
| Reduction of Interconnect Delay and Resistance While Minimizing Grid Area in GNR-Based VLSI Routing Problem S Das, DK Das, S Pandit Emerging Electronic Devices, Circuits and Systems: Select Proceedings of …, 2023 | 1 | 2023 |
| Reliability aware global routing of graphene nanoribbon based interconnect S Das, DK Das, S Pandit International Symposium on VLSI Design and Test, 373-386, 2022 | 1 | 2022 |
| A close encounter with Random Numbers S Das, P Dasgupta, A Pandey, P Roy Proceedings of the 2015 Third International Conference on Computer …, 2015 | 1 | 2015 |
| Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars P Dhal, A Deb, S Das, DK Das 2024 28th International Symposium on VLSI Design and Test (VDAT), 1-7, 2024 | | 2024 |
| Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation S Das, A Deb, P Fiser, DK Das 2024 27th Euromicro Conference on Digital System Design (DSD), 11-18, 2024 | | 2024 |
| Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring S Das, A Deb, P Fiser 2023 International Symposium on Devices, Circuits and Systems (ISDCS) 1, 01-06, 2023 | | 2023 |
| Crosstalk Aware Global Routing of Graphene Nanoribbon Based Circuits S Das, S Pandit, DK Das 2019 IEEE 19th International Conference on Nanotechnology (IEEE-NANO), 243-248, 2019 | | 2019 |
| Floorplanning in Graphene Nanoribbon (GNR) Based Circuits S Das, DK Das 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 293-298, 2018 | | 2018 |
| Algorithms for rotation symmetric Boolean functions S Das, S Ghosh, P Dasgupta, S Sensarma International Journal of Information and Coding Theory 2 (4), 238-265, 2014 | | 2014 |
| An Approach to Simplify Reversible Logic Circuits P Roy, S Das, S Sensarma International Journal of Advanced Computer Research 2 (3), 1, 2012 | | 2012 |
Petr FišerCzech Technical University in Prague, Faculty of Information TechnologyVerified email at fit.cvut.cz
