| Federated Learning with Non-IID Data Y Zhao, M Li, L Lai, N Suda, D Civin, V Chandra arXiv preprint arXiv:1806.00582, 2018 | 3217 | 2018 |
| Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ... Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 729 | 2016 |
| Bit fusion: Bit-level dynamically composable architecture for accelerating deep neural network H Sharma, J Park, N Suda, L Lai, B Chau, JK Kim, V Chandra, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 661 | 2018 |
| Hello Edge: Keyword Spotting on Microcontrollers Y Zhang, N Suda, L Lai, V Chandra arXiv preprint arXiv:1711.07128, 2017 | 559 | 2017 |
| CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs L Lai, N Suda, V Chandra arXiv preprint arXiv:1801.06601, 2018 | 509 | 2018 |
| Scalable and modularized RTL compilation of convolutional neural networks onto FPGA Y Ma, N Suda, Y Cao, J Seo, S Vrudhula 2016 26th International Conference on Field Programmable Logic and …, 2016 | 226 | 2016 |
| Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations L Lai, N Suda, V Chandra arXiv preprint arXiv:1703.03073, 2017 | 138 | 2017 |
| ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler Y Ma, N Suda, Y Cao, S Vrudhula, J Seo Integration 62, 14-23, 2018 | 123 | 2018 |
| Enabling Deep Learning at the loT Edge L Lai, N Suda 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2018 | 72 | 2018 |
| SenseHAR: a robust virtual activity sensor for smartphones and wearables JV Jeyakumar, L Lai, N Suda, M Srivastava Proceedings of the 17th Conference on Embedded Networked Sensor Systems, 15-28, 2019 | 64 | 2019 |
| Dream Distillation: A Data-Independent Model Compression Framework K Bhardwaj, N Suda, R Marculescu arXiv preprint arXiv:1905.07072, 2019 | 59 | 2019 |
| A Low-Noise Output Capacitorless Low-Dropout Regulator With a Switched-RC Bandgap Reference R Magod, N Suda, V Ivanov, R Balasingam, B Bakkaloglu IEEE Transactions on Power Electronics 32 (4), 2856-2864, 2017 | 57 | 2017 |
| Privynet: A flexible framework for privacy-preserving deep neural network training M Li, L Lai, N Suda, V Chandra, DZ Pan arXiv preprint arXiv:1709.06161, 2017 | 56 | 2017 |
| Collapsible linear blocks for super-efficient super resolution K Bhardwaj, M Milosavljevic, L O'Neil, D Gope, R Matas, A Chalfin, ... Proceedings of Machine Learning and Systems 4, 529-547, 2022 | 43 | 2022 |
| Not All Ops Are Created Equal! L Lai, N Suda, V Chandra arXiv preprint arXiv:1801.04326, 2018 | 34 | 2018 |
| EdgeAl: A Vision for Deep Learning in the IoT Era K Bhardwaj, N Suda, R Marculescu IEEE Design & Test 38 (4), 37-43, 2019 | 33 | 2019 |
| Machine Learning on ARM Cortex-M Microcontrollers N Suda, D Loh Arm Ltd.: Cambridge, UK, 2019 | 29 | 2019 |
| Spiking neural network S Naveen, V Chandra, BT Cline, SP Sinha, S Das US Patent 10,922,608, 2021 | 23 | 2021 |
| A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation N Suda, J Suh, N Hakim, Y Cao, B Bakkaloglu IEEE Transactions on Circuits and Systems I: Regular Papers 63 (2), 181-190, 2016 | 23 | 2016 |
| A 0.5-V low power analog front-end for heart-rate detector N Suda, PV Nishanth, D Basak, D Sharma, RP Paily Analog Integrated Circuits and Signal Processing 81, 417-430, 2014 | 20 | 2014 |
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