| Exploring the performance of 3-D nanosheet FET in inversion and junctionless modes: Device and circuit-level analysis and comparison VB Sreenivasulu, AK Neelam, SR Kola, J Singh, Y Li IEEE Access 11, 90421-90429, 2023 | 31 | 2023 |
| Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers SR Kola, N Thoti 2020 International Conference on Simulation of Semiconductor Processes and …, 2020 | 21 | 2020 |
| Effects of spacer and single-charge trap on voltage transfer characteristics of gate-all-around silicon nanowire CMOS devices and circuits SR Kola, Y Li, N Thoti 2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO), 217-220, 2020 | 20 | 2020 |
| Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps SR Kola, Y Li, N Thoti Journal of Computational Electronics 19, 253-262, 2020 | 19 | 2020 |
| A machine learning approach to modeling intrinsic parameter fluctuation of gate-all-around Si nanosheet MOSFETs R Butola, Y Li, SR Kola IEEE Access 10, 71356-71369, 2022 | 18 | 2022 |
| A physical-based artificial neural networks compact modeling framework for emerging FETs YS Yang, Y Li, SRR Kola IEEE Transactions on Electron Devices 71 (1), 223-230, 2023 | 16 | 2023 |
| Optimal inter-gate separation and overlapped source of multi-channel line tunnel FETs N Thoti, Y Li, SR Kola, S Samukawa IEEE Open Journal of Nanotechnology 1, 38-46, 2020 | 16 | 2020 |
| Integration design and process of 3-D heterogeneous 6T SRAM with double layer transferred Ge/2Si CFET and IGZO pass gates for 42% reduced cell size XR Yu, MH Chuang, SW Chang, WH Chang, TC Hong, CH Chiang, ... 2022 International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2022 | 15 | 2022 |
| Effects of a dual spacer on electrical characteristics and random telegraph noise of gate-all-around silicon nanowire p-type metal–oxide–semiconductor field-effect transistors SR Kola, Y Li, N Thoti Japanese Journal of Applied Physics 59 (SG), SGGA02, 2020 | 13 | 2020 |
| High-performance metal-ferroeletric-semiconductor nanosheet line tunneling field effect transistors with strained SiGe N Thoti, Y Li, SR Kola, S Samukawa 2020 international conference on simulation of semiconductor processes and …, 2020 | 10 | 2020 |
| Artificial neural network-based modeling for estimating the effects of various random fluctuations on dc/analog/rf characteristics of gaa si nanosheet fets R Butola, Y Li, SR Kola, CY Chen, MH Chuang IEEE Transactions on Microwave Theory and Techniques 70 (11), 4835-4848, 2022 | 7 | 2022 |
| Statistical 3D device simulation of full fluctuations of gate-all-around silicon nanosheet MOSFETs at sub-3-nm technology nodes SR Kola, Y Li, CY Chen, MH Chuang 2022 International Symposium on VLSI Technology, Systems and Applications …, 2022 | 7 | 2022 |
| A unified statistical analysis of comprehensive fluctuations of gate-all-around silicon nanosheet MOSFETs induced by RDF, ITF, and WKF simultaneously SR Kola, Y Li, CY Chen, MH Chuang 2022 23rd International Symposium on Quality Electronic Design (ISQED), 1-6, 2022 | 7 | 2022 |
| New proficient ferroelectric nanosheet line tunneling FETs with strained SiGe through scaled n-epitaxial layer N Thoti, Y Li, SR Kola, S Samukawa 2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO), 319-322, 2020 | 7 | 2020 |
| Intrinsic parameter fluctuation and process variation effect of vertically stacked silicon nanosheet complementary field-effect transistors SR Kola, Y Li, MH Chuang 2023 24th International Symposium on Quality Electronic Design (ISQED), 1-8, 2023 | 6 | 2023 |
| Deep learning approach to modeling and exploring random sources of gate-all-around silicon nanosheet MOSFETs R Butola, Y Li, SR Kola 2022 International Symposium on VLSI Technology, Systems and Applications …, 2022 | 6 | 2022 |
| A Comprehensive Technique based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nonosheet Transistors R Butola, Y Li, SR Kola IEEE Open Journal of Nanotechnology, 2023 | 4 | 2023 |
| Application of long short-term memory modeling technique to predict process variation effects of stacked gate-all-around Si nanosheet complementary-field effect transistors R Butola, Y Li, SR Kola, C Akbar, MH Chuang Computers and Electrical Engineering 105, 108554, 2023 | 4 | 2023 |
| Scaling limitations of line TFETs at sub-8-nm technology node N Thoti, Y Li, SR Kola 2020 International Symposium on VLSI Technology, Systems and Applications …, 2020 | 4 | 2020 |
| Statistical Device Simulation and Machine Learning of Process Variation Effects of Vertically Stacked Gate-All-Around Si Nanosheet CFETs SR Kola, Y Li, R Butola IEEE Transactions on Nanotechnology, 2024 | 3 | 2024 |
Yiming LiDepartment of Electronics and Electrical Engineering, National Yang Ming Chiao Tung UniversityVerified email at nycu.edu.tw
