| Per-die based memory refresh control based on a master controller VK Tavva US Patent 9,734,887, 2017 | 63 | 2017 |
| Way sharing set associative cache architecture CJ Janraj, TV Kalyan, T Warrier, M Mutyam 2012 25th International Conference on VLSI Design, 251-256, 2012 | 14 | 2012 |
| Word-interleaved cache: An energy efficient data cache architecture TV Kalyan, M Mutyam Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | 13 | 2008 |
| Efgr: An enhanced fine granularity refresh feature for high-performance ddr4 dram devices VK Tavva, R Kasha, M Mutyam ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 1-26, 2014 | 11 | 2014 |
| Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time TV Kalyan, K Ravi, M Mutyam 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 598-603, 2014 | 8 | 2014 |
| Exploiting variable cycle transmission for energy-efficient on-chip interconnect design TV Kalyan, M Mutyam, PVS Rao 21st international conference on VLSI design (VLSID 2008), 235-241, 2008 | 8 | 2008 |
| Write management for increasing non-volatile memory reliability S Sethuraman, VK Tavva, AJ McPadden, H Hunter US Patent 10,379,784, 2019 | 6 | 2019 |
| Temperature aware adaptations for improved read reliability in STT-MRAM memory subsystem S Sethuraman, VK Tavva, K Rajamani, CK Subramanian, KH Kim, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 5 | 2020 |
| Write management for increasing non-volatile memory reliability S Sethuraman, VK Tavva, AJ McPadden, H Hunter US Patent 10,949,122, 2021 | 4 | 2021 |
| DRAM bank activation management D Parikh, SJ Powell, VK Tavva US Patent 10,572,168, 2020 | 4 | 2020 |
| Data remapping for an energy efficient burst chop in DRAM memory systems S Jagathrakshakan, VK Tavva, M Mutyam Proceedings of the 23rd international conference on Parallel architectures …, 2014 | 4 | 2014 |
| Method and system to improve read reliability in memory devices S Sethuraman, K Rajamani, VK Tavva, H Hunter, C Subramanian US Patent 11,074,968, 2021 | 3 | 2021 |
| Scope resolution tag buffer to reduce cache miss latency SB Purushotham, N Miriyalu, VK Tavva US Patent 10,831,659, 2020 | 3 | 2020 |
| Techniques to improve write and retention reliability of STT-MRAM memory subsystem S Sethuraman, VK Tavva, MB Srinivas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 2 | 2021 |
| Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM Memories D Chinnakkonda, VK Tavva, MB Srinivas Memories-Materials, Devices, Circuits and Systems 4, 100058, 2023 | 1 | 2023 |
| DRAM bank activation management D Parikh, SJ Powell, VK Tavva US Patent 11,042,312, 2021 | 1 | 2021 |
| A scalable and energy-efficient concurrent binary search tree with fatnodes P Alapati, VK Tavva, M Mutyam IEEE Transactions on Sustainable Computing 5 (4), 468-484, 2020 | 1 | 2020 |
| TENDRA: Targeted Endurance Attack on STT-RAM LLC P Sinha, ML Sai, S Das, VK Tavva IEEE Embedded Systems Letters, 2024 | | 2024 |
| Exploring the Potential of a 1T-1M HfOX-Based Resistive Switching Device for Articulating Artificial Neural Network Hardware S Gupta, MS Yadav, VK Tavva, B Rawat 2024 International Semiconductor Conference (CAS), 337-340, 2024 | | 2024 |
| PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC P Sinha, KP BV, S Das, VK Tavva Proceedings of the International Symposium on Memory Systems, 89-103, 2024 | | 2024 |
Madhu MutyamProfessor, Department of CSE, Indian Institute of Technology MadrasVerified email at cse.iitm.ac.in