| ITT-RNA: Imperfection tolerable training for RRAM-crossbar-based deep neural-network accelerator Z Song, Y Sun, L Chen, T Li, N Jing, X Liang, L Jiang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 25 | 2020 |
| Sneak-path based test and diagnosis for 1R RRAM crossbar using voltage bias technique T Li, X Bi, N Jing, X Liang, L Jiang Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 25 | 2017 |
| Container-code recognition system based on computer vision and deep neural networks Y Liu, T Li, L Jiang, X Liang AIP Conference Proceedings 1955 (1), 2018 | 13 | 2018 |
| Gpnpu: Enabling efficient hardware-based direct convolution with multi-precision support in gpu tensor cores Z Song, J Wang, T Li, L Jiang, J Ke, X Liang, N Jing 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 11 | 2020 |
| Hubpa: High utilization bidirectional pipeline architecture for neuromorphic computing H Ji, L Jiang, T Li, N Jing, J Ke, X Liang Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 7 | 2019 |
| A novel test method for metallic CNTs in CNFET-based SRAMs T Li, F Xie, X Liang, Q Xu, K Chakrabarty, N Jing, L Jiang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 7 | 2015 |
| On microarchitectural modeling for CNFET-based circuits T Li, H Chen, W Qian, X Liang, L Jiang 2015 28th IEEE International System-on-Chip Conference (SOCC), 356-361, 2015 | 5 | 2015 |
| Timing-driven placement for carbon nanotube circuits C Wang, L Jiang, S Hu, T Li, X Liang, N Jing, W Qian 2015 28th IEEE International System-on-Chip Conference (SOCC), 362-367, 2015 | 5 | 2015 |
| CNFET-based high throughput SIMD architecture L Jiang, T Li, N Jing, NS Kim, M Guo, X Liang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 4 | 2017 |
| Fault clustering technique for 3D memory BISR T Li, Y Han, X Liang, HHS Lee, L Jiang Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 4 | 2017 |
| CNFET-based high throughput register file architecture T Li, L Jiang, N Jing, NS Kim, X Liang 2016 IEEE 34th International Conference on Computer Design (ICCD), 662-669, 2016 | 4 | 2016 |
| In-growth test for monolithic 3D integrated SRAM P Pang, Y Zhang, T Li, SK Lim, Q Chen, X Liang, L Jiang 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 569-572, 2018 | 3 | 2018 |
| Defect tolerance for CNFET-based SRAMs T Li, L Jiang, X Liang, Q Xu, K Chakrabarty 2016 IEEE International Test Conference (ITC), 1-9, 2016 | 3 | 2016 |
| A FPGA friendly approximate computing framework with hybrid Neural networks H Song, X Song, T Li, N Jing, X Liang, L Jiang IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND …, 2016 | 3 | 2016 |
| A systematic FPGA acceleration design for applications based on convolutional neural networks H Dong, L Jiang, T Li, X Liang AIP Conference Proceedings 1955 (1), 2018 | 2 | 2018 |
| Application of 3D reconstruction system in diabetic foot ulcer injury assessment J Li, L Jiang, T Li, X Liang AIP Conference Proceedings 1955 (1), 2018 | 2 | 2018 |
