The greendroid mobile application processor: An architecture for silicon's dark future N Goulding-Hotta, J Sampson, G Venkatesh, S Garcia, J Auricchio, ... IEEE Micro 31 (2), 86-95, 2011 | 220 | 2011 |
ORION3. 0: A comprehensive NoC router estimation tool AB Kahng, B Lin, S Nath IEEE Embedded Systems Letters 7 (2), 41-45, 2015 | 153 | 2015 |
ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap JA Carballo, WTJ Chan, PA Gargini, AB Kahng, S Nath 2014 IEEE 32nd international conference on computer design (ICCD), 139-146, 2014 | 130 | 2014 |
Redefining the Role of the CPU in the Era of CPU-GPU Integration M Arora, S Nath, S Mazumdar, SB Baden, DM Tullsen IEEE Micro 32 (6), 4-16, 2012 | 86 | 2012 |
SI for free: machine learning of interconnect coupling delay and transition effects AB Kahng, M Luo, S Nath 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2015 | 82 | 2015 |
BEOL stack-aware routability prediction from placement using data mining techniques WTJ Chan, Y Du, AB Kahng, S Nath, K Samadi 2016 IEEE 34th international conference on computer design (ICCD), 41-48, 2016 | 79 | 2016 |
A deep learning methodology to proliferate golden signoff timing SS Han, AB Kahng, S Nath, AS Vydyanathan 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 76 | 2014 |
Explicit modeling of control and data for improved NoC router estimation AB Kahng, B Lin, S Nath Proceedings of the 49th Annual Design Automation Conference, 392-397, 2012 | 73 | 2012 |
Learning-based approximation of interconnect delay and slew in signoff timing tools AB Kahng, S Kang, H Lee, S Nath, J Wadhwani 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2013 | 64 | 2013 |
Learning-based prediction of embedded memory timing failures during initial floorplan design WTJ Chan, KY Chung, AB Kahng, ND MacDonald, S Nath 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 178-185, 2016 | 42 | 2016 |
Rl-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning YC Lu, S Nath, V Khandelwal, SK Lim 2021 58th ACM/IEEE Design Automation Conference (DAC), 733-738, 2021 | 40 | 2021 |
On potential design impacts of electromigration awareness AB Kahng, S Nath, TS Rosing 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 527-532, 2013 | 40 | 2013 |
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction K Han, J Li, AB Kahng, S Nath, J Lee Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 39 | 2015 |
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap WTJ Chan, AB Kahng, S Nath, I Yamamoto 2014 IEEE 32nd International Conference on Computer Design (ICCD), 153-160, 2014 | 31 | 2014 |
Enhanced metamodeling techniques for high-dimensional IC design estimation problems AB Kahng, B Lin, S Nath 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 29 | 2013 |
High-dimensional metamodeling for prediction of clock tree synthesis outcomes AB Kahng, B Lin, S Nath 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2013 | 28 | 2013 |
OCV-aware top-level clock tree optimization TB Chan, K Han, AB Kahng, JG Lee, S Nath Proceedings of the 24th edition of the great lakes symposium on VLSI, 33-38, 2014 | 26 | 2014 |
3DIC benefit estimation and implementation guidance from 2DIC implementation WTJ Chan, S Nath, AB Kahng, Y Du, K Samadi Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 22 | 2015 |
Why are graph neural networks effective for eda problems? H Ren, S Nath, Y Zhang, H Chen, M Liu Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 20 | 2022 |
Doomed run prediction in physical design by exploiting sequential flow and graph learning YC Lu, S Nath, V Khandelwal, SK Lim 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 17 | 2021 |