| Low-current perpendicular domain wall motion cell for scalable high-speed MRAM S Fukami, T Suzuki, K Nagahara, N Ohshima, Y Ozaki, S Saito, R Nebashi, ... 2009 Symposium on VLSI Technology, 230-231, 2009 | 215 | 2009 |
| High critical currents in epitaxial YBa2Cu3O7−x thin films on silicon with buffer layers XD Wu, A Inam, MS Hegde, B Wilkens, CC Chang, DM Hwang, L Nazar, ... Applied physics letters 54 (8), 754-756, 1989 | 146 | 1989 |
| A 90nm 12ns 32Mb 2T1MTJ MRAM R Nebashi, N Sakimura, H Honjo, S Saito, Y Ito, S Miura, Y Kato, K Mori, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 145 | 2009 |
| Preparation of epitaxial ABO3 perovskite‐type oxide thin films on a (100)MgAl2O4/Si substrate S Matsubara, S Miura, Y Miyasaka, N Shohata Journal of applied physics 66 (12), 5826-5832, 1989 | 119 | 1989 |
| Atomic configuration of hydrogenated and clean Si(110) surfaces AT H. Ampo, S. Miura, K. Kato, Y. Ohkawa Physical Review B 34, 2329, 1986 | 114 | 1986 |
| Formation of surface superstructures by heat treatments on Ni-contaminated surface of Si (110) T Ichinokawa, H Ampo, S Miura, A Tamura Physical Review B 31 (8), 5183, 1985 | 114 | 1985 |
| 10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications N Sakimura, Y Tsuji, R Nebashi, H Honjo, A Morioka, K Ishihara, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 107 | 2014 |
| A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture S Matsunaga, S Miura, H Honjou, K Kinoshita, S Ikeda, T Endoh, H Ohno, ... 2012 Symposium on VLSI Circuits (VLSIC), 44-45, 2012 | 107 | 2012 |
| Structural and electrical properties of liquid phase epitaxially grown Y1Ba2Cu3Ox films S Miura, K Hashimoto, F Wang, Y Enomoto, T Morishita Physica C: Superconductivity 278 (3-4), 201-206, 1997 | 104 | 1997 |
| A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme T Ohsawa, H Koike, S Miura, H Honjo, K Kinoshita, S Ikeda, T Hanyu, ... IEEE Journal of Solid-State Circuits 48 (6), 1511-1520, 2013 | 94 | 2013 |
| Electronic device substrate using silicon semiconductor substrate S Matsubara, Y Miyasaka, S Miura US Patent 5,084,438, 1992 | 91 | 1992 |
| Si (100) 2× n structures induced by Ni contamination K Kato, T Ide, S Miura, A Tamura, T Ichinokawa Surface science 194 (1-2), L87-L94, 1988 | 91 | 1988 |
| Epitaxial Y‐Ba‐Cu‐O films on Si with intermediate layer by rf magnetron sputtering S Miura, T Yoshitake, S Matsubara, Y Miyasaka, N Shohata, T Satoh Applied physics letters 53 (20), 1967-1969, 1988 | 90 | 1988 |
| Magnetic random access memory circuit S Miura, H Numata US Patent 6,191,972, 2001 | 88 | 2001 |
| Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... IEEE Journal of Solid-State Circuits 50 (2), 476-489, 2014 | 73 | 2014 |
| First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning … SM H. Honjo, T. V. A. Nguyen, T. Watanabe, N. Nasuno, C. Zhang, T. Tanigawa 2019 IEEE International Electron Devices Meeting (IEDM), 28.5. 1-28.5. 4, 2019 | 72 | 2019 |
| Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating M Natsui, D Suzuki, N Sakimura, R Nebashi, Y Tsuji, A Morioka, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 70 | 2013 |
| Tunneling study of clean and oriented Y-Ba-Cu-O and Bi-Sr-Ca-Cu-O surfaces JS Tsai, I Takeuchi, J Fujita, S Miura, T Terashima, Y Bando, K Iijima, ... Physica C: superconductivity 157 (3), 537-550, 1989 | 68 | 1989 |
| Observation of gap anisotropy in YBa2Cu3O7− δ by tunneling JS Tsai, I Takeuchi, J Fujita, T Yoshitake, S Miura, S Tanaka, T Terashima, ... Physica C: Superconductivity 153, 1385-1386, 1988 | 67 | 1988 |
| 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0 ns/200ps wake-up/power-off times T Ohsawa, H Koike, S Miura, H Honjo, K Tokutome, S Ikeda, T Hanyu, ... 2012 symposium on VLSI circuits (VLSIC), 46-47, 2012 | 66 | 2012 |
Hideo OhnoTohoku UniversityVerified email at riec.tohoku.ac.jp