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LIANG YUHUA
LIANG YUHUA
Verified email at xidian.edu.cn
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Cited by
Year
A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- CMOS for Medical Implant Devices
Z Zhu, Y Liang
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (9), 2167-2176, 2015
1602015
A 14-b 20-MS/s 78.8 dB-SNDR energy-efficient SAR ADC with background mismatch calibration and noise-reduction techniques for portable medical ultrasound systems
Y Liang, C Li, S Liu, Z Zhu
IEEE Transactions on Biomedical Circuits and Systems 16 (2), 200-210, 2022
702022
Analysis of DIBL effect and negative resistance performance for NCFET based on a compact SPICE model
Y Liang, X Li, SK Gupta, S Datta, V Narayanan
IEEE Transactions on Electron Devices 65 (12), 5525-5529, 2018
692018
A 625kHz-BW, 79.3 dB-SNDR second-order noise-shaping SAR ADC using high-efficiency error-feedback structure
P Yi, Y Liang, S Liu, N Xu, L Fang, Y Hao
IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 859-863, 2021
652021
A 9.1 ENOB 200MS/s asynchronous SAR ADC with hybrid single-ended/differential DAC in 55-nm CMOS for image sensing signals
Y Liang, R Ding, Z Zhu
IEEE Sensors Journal 18 (17), 7130-7140, 2018
582018
A reconfigurable 12-to-18-Bit dynamic zoom ADC with Pole-optimized technique
Y Liang, J Ren, L Chen, H Lan, J Song, S Song, Z Zhu
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (5), 1940-1948, 2023
492023
Utilization of negative-capacitance FETs to boost analog circuit performances
Y Liang, Z Zhu, X Li, SK Gupta, S Datta, V Narayanan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (12 …, 2019
462019
A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- m CMOS
Y Xie, Y Liang, M Liu, S Liu, Z Zhu
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (1), 26-30, 2018
462018
Influence of body effect on sample-and-hold circuit design using negative capacitance FET
Y Liang, X Li, S George, S Srinivasa, Z Zhu, SK Gupta, S Datta, ...
IEEE Transactions on Electron Devices 65 (9), 3909-3914, 2018
452018
Mismatch of ferroelectric film on negative capacitance FETs performance
Y Liang, Z Zhu, X Li, SK Gupta, S Datta, V Narayanan
IEEE Transactions on Electron Devices 67 (3), 1297-1304, 2020
312020
Lowering area overheads for FeFET-based energy-efficient nonvolatile flip-flops
X Li, S George, Y Liang, K Ma, K Ni, A Aziz, SK Gupta, J Sampson, ...
IEEE Transactions on Electron Devices 65 (6), 2670-2674, 2018
312018
A time-domain reconfigurable second-order noise shaping ADC with single fan-out gated delay cells
Z Yu, Y Liang, H Lan, L Chen, J Song, S Song, Z Zhu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (6), 902-905, 2023
212023
Radio frequency analog-to-digital converters: Systems and circuits review
D Li, X Zhao, S Liu, M Liu, R Ding, Y Liang, Z Zhu
Microelectronics Journal 119, 105331, 2022
182022
A 0.1–3.5-GHz inductorless noise-canceling CMOS LNA with IIP3 optimization technique
R Zhou, S Liu, J Liu, Y Liang, Z Zhu
IEEE Transactions on Microwave Theory and Techniques 70 (6), 3234-3243, 2022
172022
SAR ADC architecture with 98.8% reduction in switching energy over conventional scheme
Y Liang, Z Zhu, R Ding
Analog Integrated Circuits and Signal Processing 84, 89-96, 2015
152015
A 10bit 20 kS/s 17.7 nW 9.1 ENOB reference-insensitive SAR ADC in 0.18 μm CMOS
Y Liang, Z Zhu
Microelectronics Journal 73, 24-29, 2018
142018
A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS
Z Yu, Y Liang, S Liu
Microelectronics Journal 117, 105253, 2021
112021
A 0.6 V 31 nW 25 ppm/° C MOSFET-only sub-threshold voltage reference
Z Zhu
Microelectronics journal 66, 25-30, 2017
112017
A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS
Y Liang, Z Zhu, R Ding
Microelectronics Journal 46 (10), 988-995, 2015
112015
A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique
L Yuhua, Z Zirui, LIU Shubin, LI Dengquan, D Ruixue, ZHU Zhangming
Chinese Journal of Electronics 30 (5), 853-860, 2021
92021
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