| Design automation for application-specific on-chip interconnects: A survey A Cilardo, E Fusella Integration 52, 102-121, 2016 | 44 | 2016 |
| PhoNoCMap: An application mapping tool for photonic networks-on-chip E Fusella, A Cilardo 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 289-292, 2016 | 33 | 2016 |
| Crosstalk-aware automated mapping for optical networks-on-chip E Fusella, A Cilardo ACM Transactions on Embedded Computing Systems (TECS) 16 (1), 1-26, 2016 | 32 | 2016 |
| H²ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology E Fusella, A Cilardo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 330-343, 2016 | 32 | 2016 |
| Minimizing power loss in optical networks-on-chip through application-specific mapping E Fusella, A Cilardo Microprocessors and Microsystems 43, 4-13, 2016 | 30 | 2016 |
| Automated synthesis of FPGA-based heterogeneous interconnect topologies A Cilardo, E Fusella, L Gallo, A Mazzeo 2013 23rd International Conference on Field programmable Logic and …, 2013 | 29 | 2013 |
| Exploring manycore architectures for next-generation HPC systems through the MANGO approach J Flich, G Agosta, P Ampletzer, DA Alonso, C Brandolese, E Cappe, ... Microprocessors and Microsystems 61, 154-170, 2018 | 24 | 2018 |
| Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems A Cilardo, E Fusella, L Gallo, A Mazzeo 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 24 | 2014 |
| Lighting up on-chip communications with photonics: Design tradeoffs for optical NoC architectures E Fusella, A Cilardo IEEE Circuits and Systems Magazine 16 (3), 4-14, 2016 | 23 | 2016 |
| Exploiting concurrency for the automated synthesis of MPSoC interconnects A Cilardo, E Fusella, L Gallo, A Mazzeo ACM Transactions on Embedded Computing Systems (TECS) 14 (3), 1-24, 2015 | 20 | 2015 |
| Reducing power consumption of lasers in photonic NoCs through application-specific mapping E Fusella, A Cilardo ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (2), 1-11, 2018 | 12 | 2018 |
| Crosstalk-aware mapping for tile-based optical network-on-chip E Fusella, A Cilardo 2015 IEEE 17th International Conference on High Performance Computing and …, 2015 | 12 | 2015 |
| Lattice-based turn model for adaptive routing E Fusella, A Cilardo IEEE Transactions on Parallel and Distributed Systems 29 (5), 1117-1130, 2017 | 11 | 2017 |
| Path setup for hybrid NoC architectures exploiting flooding and standby E Fusella, J Flich, A Cilardo IEEE Transactions on Parallel and Distributed Systems 28 (5), 1403 - 1416, 2016 | 11 | 2016 |
| Automated design space exploration for FPGA-based heterogeneous interconnects A Cilardo, E Fusella, L Gallo, A Mazzeo, N Mazzocca Design Automation for Embedded Systems 18, 157-170, 2014 | 10 | 2014 |
| On the design of a path-setup architecture for exploiting hybrid photonic-electronic NoCs E Fusella, J Flich, A Cilardo, A Mazzeo 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High …, 2015 | 6 | 2015 |
| Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip E Fusella, A Cilardo, A Mazzeo 2015 25th International Conference on Field Programmable Logic and …, 2015 | 4 | 2015 |
| Improving Deep Learning with a customizable GPU-like FPGA-based accelerator M Gagliardi, E Fusella, A Cilardo 2018 14th Conference on Ph. D. Research in Microelectronics and Electronics …, 2018 | 2 | 2018 |
| Understanding turn models for adaptive routing: The modular approach E Fusella, A Cilardo 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 1 | 2018 |
| Deeply heterogeneous many-accelerator infrastructure for HPC architecture exploration J Flich, A Cilardo, M Kovaç, R Tornero, M Gagliardi, E Fusella, ... Parallel Computing is Everywhere, 381-389, 2018 | 1 | 2018 |
Alessandro CilardoU. of Naples Federico II-For full details, please refer to http://wpage.unina.it/acilardoVerified email at unina.it