| Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model MK Ieong, PM Solomon, SE Laux, HSP Wong, D Chidambarrao International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 256 | 1998 |
| Vertical fin-fet mos devices D Chidambarrao, J Beintner, R Divakaruni US Patent 7,683,428, 2010 | 254 | 2010 |
| High performance strained silicon FinFETs device and method for forming same SW Bedell, KK Chan, D Chidambarrao, SH Christianson, JO Chu, ... US Patent 7,705,345, 2010 | 253 | 2010 |
| Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing HS Yang, R Malik, S Narasimha, Y Li, R Divakaruni, P Agnello, S Allen, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 238 | 2004 |
| Methods and system for analysis and management of parametric yield JA Culp, P Chang, D Chidambarrao, P Elakkumanan, J Hibbeler, ... US Patent 8,042,070, 2011 | 231 | 2011 |
| Structure and method to improve channel mobility by gate electrode stress modification MP Belyansky, D Chidambarrao, OH Dokumaci, BB Doris, O Gluschenkov US Patent 6,977,194, 2005 | 218 | 2005 |
| Stress inducing spacers D Chidambarrao, OH Dokumaci, BB Doris, JA Mandelman, X Baie US Patent 6,825,529, 2004 | 210 | 2004 |
| Strained finFETs and method of manufacture D Chidambarrao, OH Dokumaci, OG Gluschenkov US Patent 7,198,995, 2007 | 193 | 2007 |
| High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ... 2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014 | 192 | 2014 |
| Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions H Chen, D Chidambarrao, OG Gluschenkov, AL Steegen, HS Yang US Patent 6,891,192, 2005 | 184 | 2005 |
| Strained finFET CMOS device structures BB Doris, D Chidambarrao, M Ieong, JA Mandelman US Patent 7,388,259, 2008 | 171 | 2008 |
| High performance stress-enhanced MOSFETs using Si: C and SiGe epitaxial source/drain and method of manufacture H Chen, D Chidambarrao, OH Dokumaci US Patent 7,303,949, 2007 | 169 | 2007 |
| SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device BB Doris, D Chidambarrao, X Baie, JA Mandelman, DK Sadana, ... US Patent 6,717,216, 2004 | 167 | 2004 |
| Isolation structures for imposing stress patterns D Chidambarrao, OH Dokumaci, BB Doris, JA Mandelman US Patent 6,974,981, 2005 | 154 | 2005 |
| High performance CMOS device structures and method of manufacture BB Doris, D Chidambarrao, SH Ku US Patent 7,279,746, 2007 | 144 | 2007 |
| Stress inducing spacers D Chidambarrao, OH Dokumaci, BB Doris, JA Mandelman, X Baie US Patent 7,374,987, 2008 | 142 | 2008 |
| Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby D Chidambarrao, O Dokumaci US Patent 7,060,539, 2006 | 135 | 2006 |
| Structure and method for mobility enhanced MOSFETs with unalloyed silicide Y Liu, D Chidambarrao, O Gluschenkov, JR Holt, RT Mo, K Rim US Patent 8,217,423, 2012 | 132 | 2012 |
| Strain effects on device characteristics: Implementation in drift-diffusion simulators JL Egley, D Chidambarrao Solid-State Electronics 36 (12), 1653-1664, 1993 | 132 | 1993 |
| Silicon device on Si: C-OI and SGOI and method of manufacture D Chidambarrao, OH Dokumaci, OG Gluschenkov US Patent 7,247,534, 2007 | 123 | 2007 |
