A cryogenic CMOS chip for generating control signals for multiple qubits SJ Pauka, K Das, R Kalra, A Moini, Y Yang, M Trainer, A Bousquet, ... Nature Electronics 4 (1), 64-70, 2021 | 183 | 2021 |
A cryogenic interface for controlling many qubits SJ Pauka, K Das, R Kalra, A Moini, Y Yang, M Trainer, A Bousquet, ... arXiv preprint arXiv:1912.01299, 2019 | 51 | 2019 |
Characterizing quantum devices at scale with custom cryo-CMOS SJ Pauka, K Das, JM Hornibrook, GC Gardner, MJ Manfra, MC Cassidy, ... Physical Review Applied 13 (5), 054072, 2020 | 36 | 2020 |
Effect of deep cryogenic temperature on silicon-on-insulator CMOS mismatch: A circuit designer’s perspective K Das, T Lehmann Cryogenics 62, 84-93, 2014 | 28 | 2014 |
Sub-nanoampere one-shot single electron transistor readout electrometry below 10 kelvin K Das, T Lehmann, AS Dzurak IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2816-2824, 2014 | 17 | 2014 |
SOS current mirror matching at 4K: A brief study K Das, T Lehmann Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 17 | 2010 |
Implant electronics for intraocular epiretinal neuro-stimulators T Lehmann, NH Lovell, GJ Suaning, P Preston, YT Wong, N Dommel, ... 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 352-355, 2008 | 15 | 2008 |
A cryo-CMOS voltage reference in 28-nm FDSOI Y Yang, K Das, A Moini, DJ Reilly IEEE Solid-State Circuits Letters 3, 186-189, 2020 | 11 | 2020 |
Low temperature microelectronics design for digital readout of single electron transistor electrometry K Das UNSW Sydney, 2013 | 11 | 2013 |
Low power fast cryogenic CMOS circuit for digital readout of single electron transistor K Das, T Lehmann 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 11 | 2011 |
4.2 K CMOS circuit design for digital readout of single electron transistor electrometry K Das, T Lehmann, MT Rahman 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 865-868, 2010 | 11 | 2010 |
Cryo-CMOS band-gap reference circuits for quantum computing Y Yang, K Das, A Moini, DJ Reilly arXiv preprint arXiv:1910.01217, 2019 | 6 | 2019 |
A cryogenic interface for controlling many qubits. 2019 SJ Pauka, K Das, R Kalra, A Moini, Y Yang, M Trainer, A Bousquet, ... Available: arXiv, 1912 | 6 | 1912 |
Cryogenic floating-gate CMOS circuits for quantum control J Hasler, N Dick, K Das, B Degnan, A Moini, D Reilly IEEE Transactions on Quantum Engineering 2, 1-10, 2021 | 5 | 2021 |
A cryogenic single electron transistor readout circuit: Practical issues and measurement considerations K Das, T Lehmann 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 1359-1362, 2012 | 5 | 2012 |
Charge locking circuits and control system for qubits K Das, A Moini, DJ Reilly US Patent 11,509,310, 2022 | 2 | 2022 |
Spin Qubits with Scalable milli-kelvin CMOS Control SK Bartee, W Gilbert, K Zuo, K Das, T Tanttu, CH Yang, ND Stuyck, ... arXiv preprint arXiv:2407.15151, 2024 | 1 | 2024 |
Mismatch insensitive automatic tuning control for the single electron transistor readout circuit K Das, T Lehmann 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013 | 1 | 2013 |
Sub-kelvin temperature gradient system for scalable quantum control DJ Reilly, IDC LAMB, K Das, R Kalra US Patent App. 18/171,632, 2024 | | 2024 |
Spin Qubits with Integrated millikelvin CMOS Control S Bartee, W Gilbert, K Zuo, K Das, T Tanttu, H Yang, N Stuyck, R Kalra, ... Bulletin of the American Physical Society, 2024 | | 2024 |