| A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging K Mistry, C Allen, C Auth, B Beattie, D Bergstrom, M Bost, M Brazier, ... 2007 IEEE International Electron Devices Meeting, 247-250, 2007 | 1695 | 2007 |
| A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors T Ghani, M Armstrong, C Auth, M Bost, P Charvat, G Glass, T Hoffmann, ... IEEE International Electron Devices Meeting 2003, 11.6. 1-11.6. 3, 2003 | 1080 | 2003 |
| A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors C Auth, C Allen, A Blattner, D Bergstrom, M Brazier, M Bost, M Buehler, ... 2012 symposium on VLSI technology (VLSIT), 131-132, 2012 | 1049 | 2012 |
| 45nm high-k+ metal gate strain-enhanced transistors C Auth, A Cappellani, JS Chun, A Dalis, A Davis, T Ghani, G Glass, ... 2008 Symposium on VLSI Technology, 128-129, 2008 | 608 | 2008 |
| A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate … C Auth, A Aliyarukunju, M Asoro, D Bergstrom, V Bhagwat, J Birdsall, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.1. 1-29.1. 4, 2017 | 467 | 2017 |
| A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ... Digest. International Electron Devices Meeting,, 61-64, 2002 | 458 | 2002 |
| Amorphous etch stop for the anisotropic etching of substrates S Keating, C Auth US Patent 7,045,407, 2006 | 208 | 2006 |
| Device with stepped source/drain region profile G Curello, B Sell, S Tyagi, C Auth US Patent 7,335,959, 2008 | 100 | 2008 |
| IEDM Tech. Dig. S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ... IEDM Tech. Dig, 61, 2002 | 99 | 2002 |
| 22-nm fully-depleted tri-gate CMOS transistors C Auth Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-6, 2012 | 80 | 2012 |
| Copper-filled trench contact for transistor performance improvement KJ Kuhn, K Mistry, M Bohr, C Auth US Patent 8,258,057, 2012 | 58 | 2012 |
| Integrated circuit with improved channel stress properties and a method for making it T Hoffmann, C Auth, M Armstrong, S Cea US Patent 7,045,408, 2006 | 43 | 2006 |
| 45nm high-k+ metal gate strain-enhanced CMOS transistors C Auth 2008 IEEE Custom Integrated Circuits Conference, 379-386, 2008 | 40 | 2008 |
| Interconnect stack using self-aligned quad and double patterning for 10nm high volume manufacturing A Yeoh, A Madhavan, N Kybert, S Anand, J Shin, M Asoro, ... 2018 IEEE International Interconnect Technology Conference (IITC), 144-147, 2018 | 34 | 2018 |
| Methods for selective deposition to improve selectivity A Murthy, N Gupta, C Auth, GA Glass US Patent 7,129,139, 2006 | 30 | 2006 |
| Design-technology co-optimization of standard cell libraries on Intel 10nm process X Wang, R Kumar, SB Prakash, P Zheng, TH Wu, Q Shi, M Nabors, ... 2018 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2018 | 23 | 2018 |
| Copper-filled trench contact for transistor performance improvement KJ Kuhn, K Mistry, M Bohr, C Auth US Patent 8,766,372, 2014 | 23 | 2014 |
| Dual silicide flow for cmos SM Joshi, C Auth US Patent App. 12/646,668, 2011 | 23 | 2011 |
| Selective deposition to improve selectivity and structures formed thereby A Murthy, N Gupta, C Auth, GA Glass US Patent 7,358,547, 2008 | 17 | 2008 |
| Evolution of Transistors: Humble Beginnings to the Ubiquitous Present C Auth, A Shankar IEEE Solid-State Circuits Magazine 15 (3), 20-28, 2023 | 4 | 2023 |
