| CNTFET-based design of ternary logic gates and arithmetic circuits S Lin, YB Kim, F Lombardi IEEE transactions on nanotechnology 10 (2), 217-225, 2009 | 688 | 2009 |
| Challenges for nanoscale MOSFETs and emerging nanoelectronics YB Kim transactions on electrical and electronic materials 11 (3), 93-105, 2010 | 349 | 2010 |
| A novel CNTFET-based ternary logic gate design S Lin, YB Kim, F Lombardi 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 435-438, 2009 | 216 | 2009 |
| Design of a ternary memory cell using CNTFETs S Lin, YB Kim, F Lombardi IEEE transactions on nanotechnology 11 (5), 1019-1025, 2012 | 177 | 2012 |
| A novel design methodology to optimize the speed and power of the CNTFET circuits YB Kim, YB Kim, F Lombardi 2009 52nd IEEE international midwest symposium on circuits and systems, 1130 …, 2009 | 143 | 2009 |
| Design of a CNTFET-based SRAM cell by dual-chirality selection S Lin, YB Kim, F Lombardi IEEE Transactions on Nanotechnology 9 (1), 30-37, 2009 | 133 | 2009 |
| Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset S Lin, YB Kim, F Lombardi IEEE Transactions on Device and Materials Reliability 12 (1), 68-77, 2011 | 126 | 2011 |
| A CMOS subbandgap reference circuit with 1-V power supply voltage J Doyle, YJ Lee, YB Kim, H Wilsch, F Lombardi IEEE Journal of Solid-State Circuits 39 (1), 252-255, 2004 | 118 | 2004 |
| Standby leakage power reduction technique for nanoscale CMOS VLSI systems HJ Jeon, YB Kim, M Choi IEEE transactions on instrumentation and measurement 59 (5), 1127-1133, 2010 | 114 | 2010 |
| Performance evaluation of CNFET-based logic gates G Cho, YB Kim, F Lombardi, MS Choi 2009 IEEE Instrumentation and Measurement Technology Conference, 909-912, 2009 | 113 | 2009 |
| A CMOS low-power low-offset and high-speed fully dynamic latched comparator HJ Jeon, YB Kim 23rd IEEE International SOC Conference, 285-288, 2010 | 104 | 2010 |
| Design and performance evaluation of radiation hardened latches for nanoscale CMOS S Lin, YB Kim, F Lombardi IEEE transactions on very large scale integration (VLSI) systems 19 (7 …, 2010 | 99 | 2010 |
| Leakage minimization technique for nanoscale CMOS VLSI KK Kim, YB Kim, M Choi, N Park IEEE Design & Test of Computers 24 (4), 322-330, 2007 | 90 | 2007 |
| Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability S Lin, YB Kim, F Lombardi Integration 43 (2), 176-187, 2010 | 89 | 2010 |
| A novel sort error hardened 10T SRAM cells for low voltage operation IS Jung, YB Kim, F Lombardi 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 88 | 2012 |
| A new SRAM cell design using CNTFETs S Lin, YB Kim, F Lombardi, YJ Lee 2008 International SoC Design Conference 1, I-168-I-171, 2008 | 88 | 2008 |
| Fault tolerant source routing for network-on-chip YB Kim, YB Kim 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007 | 86 | 2007 |
| A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator HJ Jeon, YB Kim Analog Integrated Circuits and Signal Processing 70, 337-346, 2012 | 85 | 2012 |
| A 11-transistor nanoscale CMOS memory cell for hardening to soft errors S Lin, YB Kim, F Lombardi IEEE transactions on very large scale integration (VLSI) systems 19 (5), 900-904, 2010 | 80 | 2010 |
| Low power real time electronic neuron VLSI design using subthreshold technique YJ Lee, J Lee, YB Kim, J Ayers, A Volkovskii, A Selverston, H Abarbanel, ... 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 4, IV-744, 2004 | 75 | 2004 |
Sheng LinGoogleVerified email at ece.neu.edu