| A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS G Balamurugan, J Kennedy, G Banerjee, JE Jaussi, M Mansuri, ... IEEE Journal of Solid-State Circuits 43 (4), 1010-1019, 2008 | 211 | 2008 |
| A 10-GHz global clock distribution using coupled standing-wave oscillators F O'Mahony, CP Yue, MA Horowitz, SS Wong IEEE Journal of Solid-State Circuits 38 (11), 1813-1820, 2003 | 191 | 2003 |
| Clocking analysis, implementation and measurement techniques for high-speed data links—A tutorial B Casper, F O'Mahony IEEE Transactions on Circuits and Systems I: Regular Papers 56 (1), 17-39, 2009 | 147 | 2009 |
| A low-power, 20-Gb/s continuous-time adaptive passive equalizer R Sun, J Park, F O'Mahony, CP Yue 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 920-923, 2005 | 119 | 2005 |
| 3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS J Kim, A Balankutty, A Elshazly, YY Huang, H Song, K Yu, F O'Mahony 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 118 | 2015 |
| Modeling and analysis of high-speed I/O links G Balamurugan, B Casper, JE Jaussi, M Mansuri, F O'Mahony, J Kennedy IEEE transactions on advanced packaging 32 (2), 237-247, 2009 | 118 | 2009 |
| A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. B Casper, J Jaussi, F O'Mahony, M Mansuri, K Canagasaby, J Kennedy, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 118* | 2006 |
| A scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-lane parallel I/O in 32-nm CMOS M Mansuri, JE Jaussi, JT Kennedy, TC Hsueh, S Shekhar, ... IEEE Journal of solid-state circuits 48 (12), 3229-3242, 2013 | 114 | 2013 |
| A 4710 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS F O'Mahony, JE Jaussi, J Kennedy, G Balamurugan, M Mansuri, ... IEEE journal of solid-state circuits 45 (12), 2828-2837, 2010 | 113 | 2010 |
| A 0.6 mW/Gb/s, 6.4–7.2 Gb/s serial link receiver using local injection-locked ring oscillators in 90 nm CMOS K Hu, T Jiang, J Wang, F O'Mahony, PY Chiang IEEE Journal of Solid-State Circuits 45 (4), 899-908, 2010 | 110 | 2010 |
| 8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package W Gomes, S Khushu, DB Ingerly, PN Stover, NI Chowdhury, F O'Mahony, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 144-146, 2020 | 89 | 2020 |
| Strong Injection Locking in Low-LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver S Shekhar, M Mansuri, F O'Mahony, G Balamurugan, JE Jaussi, ... IEEE Transactions on Circuits and Systems I: Regular Papers 56 (8), 1818-1829, 2009 | 87 | 2009 |
| A 112 Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with three-tap FFE in 10-nm FinFET J Kim, A Balankutty, RK Dokania, A Elshazly, HS Kim, S Kundu, D Shi, ... IEEE Journal of Solid-State Circuits 54 (1), 29-42, 2018 | 82 | 2018 |
| Future microprocessor interfaces: Analysis, design and optimization B Casper, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, F O'Mahony, ... 2007 IEEE Custom Integrated Circuits Conference, 479-486, 2007 | 76 | 2007 |
| Ponte Vecchio: A multi-tile 3D stacked processor for exascale computing W Gomes, A Koker, P Stover, D Ingerly, S Siers, S Venkataraman, C Pelto, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 42-44, 2022 | 75 | 2022 |
| A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS J Kim, A Balankutty, R Dokania, A Elshazly, HS Kim, S Kundu, S Weaver, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 102-104, 2018 | 75 | 2018 |
| 8.1 A 224Gb/s DAC-based PAM-4 transmitter with 8-tap FFE in 10nm CMOS J Kim, S Kundu, A Balankutty, M Beach, BC Kim, S Kim, Y Liu, SK Murthy, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 126-128, 2021 | 72 | 2021 |
| A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET J Kim, S Kundu, A Balankutty, M Beach, BC Kim, ST Kim, Y Liu, SK Murthy, ... IEEE Journal of Solid-State Circuits 57 (1), 6-20, 2021 | 64 | 2021 |
| 10.5 A 5.9 pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS R Dokania, A Kern, M He, A Faust, R Tseng, S Weaver, K Yu, C Bil, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 62 | 2015 |
| The future of electrical I/O for microprocessors F O'Mahony, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, ... 2009 International Symposium on VLSI Design, Automation and Test, 31-34, 2009 | 62 | 2009 |
Bryan CasperIntelVerified email at intel.com