| Heterogeneous 2.5 D integration on through silicon interposer X Zhang, JK Lin, S Wickramanayaka, S Zhang, R Weerasekera, R Dutta, ... Applied physics reviews 2 (2), 2015 | 177 | 2015 |
| Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs R Weerasekera, LR Zheng, D Pamunuwa, H Tenhunen 2007 IEEE/ACM International Conference on Computer-Aided Design, 212-219, 2007 | 136 | 2007 |
| Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits R Weerasekera, M Grange, D Pamunuwa, H Tenhunen, LR Zheng 2009 IEEE International Conference on 3D System Integration, 1-8, 2009 | 131 | 2009 |
| Scalability of network-on-chip communication architecture for 3-D meshes AY Weldezion, M Grange, D Pamunuwa, Z Lu, A Jantsch, R Weerasekera, ... 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 114-123, 2009 | 79 | 2009 |
| CMOS high density electrical impedance biosensor array for tumor cell detection Y Chen, CC Wong, TS Pui, R Nadipalli, R Weerasekera, J Chandran, ... Sensors and Actuators B: Chemical 173, 903-907, 2012 | 70 | 2012 |
| Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance, and technological constraints R Weerasekera, D Pamunuwa, LR Zheng, H Tenhunen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 57 | 2009 |
| Synthesis of Inline Mixed Coupled Quasi-Elliptic Bandpass Filters Based onResonators S Zhang, L Zhu, R Weerasekera IEEE Transactions on Microwave Theory and Techniques 63 (10), 3487-3493, 2015 | 55 | 2015 |
| On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits R Weerasekera, M Grange, D Pamunuwa, H Tenhunen 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 42 | 2010 |
| BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems C Wang, J Zhou, R Weerasekera, B Zhao, X Liu, P Royannez, M Je IEEE Transactions on Circuits and Systems I: Regular Papers 62 (1), 139-148, 2014 | 41 | 2014 |
| Semiconductor package and method of forming the same R Weerasekera, S Bhattacharya, K Fai Chang, VS Rao US Patent 11,018,080, 0 | 31* | |
| Interconnect design and analysis for through silicon interposers (TSIs) JR Cubillo, R Weerasekera, ZZ Oo, EX Liu, B Conn, S Bhattacharya, ... 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE …, 2012 | 30 | 2012 |
| 3-D memory organization and performance analysis for multi-processor network-on-chip architecture AY Weldezion, Z Lu, R Weerasekera, H Tenhunen 2009 IEEE International Conference on 3D System Integration, 1-7, 2009 | 30 | 2009 |
| On the impact of through-silicon-via-induced stress on 65-nm CMOS devices R Weerasekera, HY Li, LW Yi, H Sanming, J Shi, J Minkyu, KH Teo IEEE Electron Device Letters 34 (1), 18-20, 2012 | 29 | 2012 |
| System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits R Weerasekera KTH, 2008 | 28 | 2008 |
| High density CMOS electrode array for high-throughput and automated cell counting TS Pui, Y Chen, CC Wong, R Nadipalli, R Weerasekera, SK Arya, H Yu, ... Sensors and Actuators B: Chemical 181, 842-849, 2013 | 25 | 2013 |
| Wire-bonded through-silicon vias with low capacitive substrate coupling AC Fischer, M Grange, N Roxhed, R Weerasekera, D Pamunuwa, ... Journal of Micromechanics and Microengineering 21 (8), 085035, 2011 | 23 | 2011 |
| High frequency characterization of inkjet printed coplanar waveguides B Shao, R Weerasekera, LR Zheng, R Liu, W Zapka, P Lindberg 2008 12th IEEE Workshop on Signal Propagation on Interconnects, 1-4, 2008 | 22 | 2008 |
| Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs) R Weerasekera, DB Pamunuwa, M Grange, H Tenhunen, LR Zheng Proc. Special Interest Workshop on 3D Integration--Design Automation and …, 2009 | 19 | 2009 |
| Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits AY Weldezion, R Weerasekera, D Pamunuwa, L Zheng, H Tenhunen DATE'09 Friday Workshops-3D Integration-Technology, Architecture, Design …, 2009 | 18 | 2009 |
| High frequency characterization and modelling of inkjet printed interconnects on flexible substrate for low-cost RFID applications B Shao, R Weerasekera, AT Woldegiorgis, LR Zheng, R Liu, W Zapka 2008 2nd Electronics System-Integration Technology Conference, 695-700, 2008 | 18 | 2008 |
Dinesh PamunuwaProfessor, University of Bristol, Royal Academy of Engineering and Microchip Senior Research ChairVerified email at bristol.ac.uk