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Siyuan Ye
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23.1 A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based …
J Gao, L Shen, H Li, S Ye, J Li, X Xu, J Cui, Y Gao, R Huang, L Ye
2023 IEEE International Solid-State Circuits Conference (ISSCC), 346-348, 2023
82023
9.1 A 2mW 70.7 dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting
S Ye, L Shen, J Gao, J Li, Z Chen, X Xu, J Cui, H Zhang, X Zhang, L Ye, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 168-170, 2024
62024
A readout circuit with current-compensation-based extended-counting ADC for 1024× 768 diode uncooled infrared imagers
S Yu, X Shi, Y Zhang, G Chen, S Ye, W Lu, Z Chen
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
32021
3.10 A 0.69/0.58-PEF 1.6 nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS
X Xu, S Ye, Y Luan, J Gao, J Li, J Cui, H Zhang, R Huang, L Shen, L Ye
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 72-74, 2024
22024
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique
Z Chen, L Shen, S Ye, J Gao, J Li, J Cui, X Xu, Y Luan, H Zhang, L Ye, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 174-176, 2024
22024
A 12.5-ppm/° C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology
X Xu, L Shen, S Ye, J Wu, Z Chen, J Gao, J Cui, Y Zhang, R Huang, L Ye
ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC …, 2023
22023
A 32-ppm/° C 0.9-nW/kHz relaxation oscillator with event-driven architecture and charge reuse technique
X Xu, S Ye, J Gao, Y Zhang, L Shen, L Ye
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1973-1977, 2022
22022
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2 dB SNDR at Nyquist Input
J Li, L Shen, S Ye, J Gao, J Cui, X Xu, Z Chen, Y Luan, Y Bao, R Huang, ...
2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024
12024
Post-layout simulation driven analog circuit sizing
X Gao, H Zhang, S Ye, M Liu, DZ Pan, L Shen, R Wang, Y Lin, R Huang
Science China Information Sciences 67 (4), 142401, 2024
12024
A Flying-Capacitor-Based Reset Scheme for Low Power Dynamic Comparator
KC Li, X Xu, J Gao, S Ye, J Cui, Y Zhang, R Huang, L Shen
IEEE Transactions on Circuits and Systems II: Express Briefs, 2024
2024
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting
S Ye, J Gao, J Li, Z Chen, X Xu, J Cui, Y Luan, L Ye, X Zhang, R Huang, ...
IEEE Journal of Solid-State Circuits, 2024
2024
A 0.41 ns CLK-OUT Delay, 0.22 mVrms Input-Referred Noise CMOS Integration Dynamic Comparator With Flipping Capacitor for Charge Reuse
KC Li, X Xu, J Gao, S Ye, J Cui, Y Zhang, R Huang, L Shen
IEEE Solid-State Circuits Letters, 2024
2024
A 0.0045 mm2 31.5uW 312.5kHz-BW 2nd-Order Noise-shaping SAR ADC with a Dynamic-BulkSwitching Single-Transistor Amplifier
J Cui, S Ye, J Gao, X Xu, Y Luan, J Li, Z Chen, Y He, R Huang, L Ye, ...
2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 373-376, 2024
2024
An Energy-Efficient, High-Resolution kT/C-Noise-Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS
J Gao, S Ye, J Li, X Xu, Z Chen, J Cui, Y Luan, R Huang, L Ye, L Shen
IEEE Journal of Solid-State Circuits, 2024
2024
A Self-Heating-Followed Non-Uniformity Calibration Circuit for Silicon Diode Uncooled IRFPA
Y Zhou, S Ye, W Lu, D Yu, Y Zhang, Z Chen
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit …, 2022
2022
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