| A silicon single-electron transistor memory operating at room temperature L Guo, E Leobandung, SY Chou Science 275 (5300), 649-651, 1997 | 600 | 1997 |
| MOSFET with super-steep retrograded island H Zhu, E Leobandung, AC Mocuta, DM Mocuta US Patent 7,723,750, 2010 | 367 | 2010 |
| Observation of quantum effects and Coulomb blockade in silicon quantum‐dot transistors at temperatures over 100 K E Leobandung, L Guo, Y Wang, SY Chou Applied physics letters 67 (7), 938-940, 1995 | 330 | 1995 |
| A room-temperature silicon single-electron metal–oxide–semiconductor memory with nanoscale floating-gate and ultranarrow channel L Guo, E Leobandung, SY Chou Applied Physics Letters 70 (7), 850-852, 1997 | 237 | 1997 |
| Single-electron floating-gate MOS memory SY Chou, L Guo, E Leobandung US Patent 6,069,380, 2000 | 185 | 2000 |
| Single hole quantum dot transistors in silicon E Leobandung, L Guo, SY Chou Applied physics letters 67 (16), 2338-2340, 1995 | 183 | 1995 |
| Process of making densely patterned silicon-on-insulator (SOI) region on a wafer E Leobandung, DK Sadana, DJ Schepis, GG Shahidi US Patent 6,214,694, 2001 | 155 | 2001 |
| Double planar gated SOI MOSFET structure JW Adkisson, JA Bracchitta, JJ Ellis-Monaghan, JB Lasky, E Leobandung, ... US Patent 6,483,156, 2002 | 145 | 2002 |
| Integration of dual workfunction metal gate CMOS devices BH Lee, E Leobandung, GG Shahidi US Patent 6,653,698, 2003 | 139 | 2003 |
| Structure and method for manufacturing MOSFET with super-steep retrograded island H Zhu, E Leobandung, AC Mocuta, DM Mocuta US Patent 7,268,049, 2007 | 135 | 2007 |
| A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch VS Basker, T Standaert, H Kawasaki, CC Yeh, K Maitra, T Yamashita, ... 2010 Symposium on VLSI Technology, 19-20, 2010 | 122 | 2010 |
| Strained silicon NMOS devices with embedded source/drain D Chidambarrao, E Leobandung, AC Mocuta, HS Yang, H Zhu US Patent 6,881,635, 2005 | 117 | 2005 |
| Stacked nanowire device with variable number of nanowire channels E Leobandung US Patent 9,257,545, 2016 | 103 | 2016 |
| Semiconductor device structure with active regions having different surface directions and methods BB Doris, O Gluschenkov, M Ieong, E Leobandung, H Zhu US Patent 7,354,806, 2008 | 103 | 2008 |
| Partially-depleted SOI technology for digital logic GG Shahidi, A Ajmera, F Assaderaghi, RJ Bolam, E Leobandung, ... 1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999 | 97 | 1999 |
| Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond Q Liu, A Yagishita, N Loubet, A Khakifirooz, P Kulkarni, T Yamamoto, ... 2010 Symposium on VLSI Technology, 61-62, 2010 | 96 | 2010 |
| RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology B Walsh, H Utomo, E Leobandung, A Mahorowala, D Mocuta, K Miyamoto, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 170-171, 2006 | 95 | 2006 |
| Channel doping impact on FinFETs for 22nm and beyond CH Lin, R Kambhampati, RJ Miller, TB Hook, A Bryant, W Haensch, ... 2012 Symposium on VLSI Technology (VLSIT), 15-16, 2012 | 90 | 2012 |
| Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer SW Bedell, AG Domenicucci, KE Fogel, E Leobandung, DK Sadana US Patent 6,991,998, 2006 | 87 | 2006 |
| High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E Leobandung, H Nayakama, D Mocuta, K Miyamoto, M Angyal, HV Meer, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 126-127, 2005 | 85 | 2005 |
