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Ramesh Chinthala
Ramesh Chinthala
Other namesC Ramesh, Chinthala Ramesh, Ramesh C
Professor of Electronics & VLSI, Amrita Vishwa Vidyapeetham
Verified email at blr.amrita.edu - Homepage
Title
Cited by
Cited by
Year
A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA, and GPU architectures
O Ferraz, S Subramaniyan, R Chinthala, J Andrade, JR Cavallaro, ...
IEEE Communications Surveys & Tutorials 24 (1), 524-556, 2021
552021
Low cost flex powered gesture detection system and its applications
P Telluri, S Manam, S Somarouthu, JM Oli, C Ramesh
2020 Second International Conference on Inventive Research in Computing …, 2020
212020
An efficient design methodology to speed up the FPGA implementation of artificial neural networks
KV Vineetha, MMSK Reddy, C Ramesh, DG Kurup
Engineering Science and Technology, an International Journal 47, 101542, 2023
82023
Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs
R Chinthala, NS Murty
2019 International Conference on Computer Communication and Informatics …, 2019
72019
Implementation of an area efficient high throughput architecture for sparse matrix LU factorization
GP Kumar, C Ramesh
2019 3rd International Conference on Electronics, Materials Engineering …, 2019
42019
An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique
N Soni, R Chinthala
2020 International Conference on Smart Electronics and Communication (ICOSEC …, 2020
32020
Complex Binary Number System-based Co-Processor Design for Signal Processing Applications
SS Santosh, TS Swaroop, T Kavya, R Chinthala
2021 5th International Conference on Electronics, Materials Engineering …, 2021
12021
Implementation of direct demodulator based on ANN using FPGA
KV Vineetha, C Ramesh, DG Kurup
Alexandria Engineering Journal 108, 730-753, 2024
2024
Enhancing BER Performance in Phase Noise using KNN-based Symbol Detection
S Krishnamurthy, M Panda, R Chinthala, R Gandhiraj
2024 15th International Conference on Computing Communication and Networking …, 2024
2024
Design and Implementation of an Efficient 32-Bit Fixed-Point Newton-Raphson Division-Based Reciprocal Computing Unit
CS Aragula, B Preethi, C Ramesh
2024 IEEE 4th International Conference on VLSI Systems, Architecture …, 2024
2024
Implementation of Neural Network Based Digital Pre-distorter for Power Amplifier Linearisation
MA Bharadwaj, C Ramesh, RVS Devi
2024 Second International Conference on Emerging Trends in Information …, 2024
2024
Cost Efficient Location Tracking and Health Monitoring System for Soldier Safety
R Jayaramu, GSK Reddy, R Chinthala, TL Purushottama, ...
2023 Global Conference on Information Technologies and Communications (GCITC …, 2023
2023
FPGA Implementation of UaL Decomposition, an alternative to the LU factorization
S Ruchitha, R Chinthala
Mathematical Statistician and Engineering Applications 71 (4), 1081-1094, 2022
2022
High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF (4)
CC Kumar, R Chinthala
2020 4th International Conference on Electronics, Materials Engineering …, 2020
2020
Sensor Data Acquisition and De-noising using FPGA
RC K Harikrishnan, H. N. Vishwas, K.V. Vineetha
International Journal of Scientific & Engineering Research 11 (8), 1673 - 1680, 2020
2020
Implementation of Blind Source Separation using FPGA
RC C.P. Anu Vyshakh, K.V. Vineetha
International Journal of Scientific & Engineering Researc 11 (9), 1098 - 1104, 2020
2020
Exploration of Cache Line Size for Sawtooth Compressed Row Storage based SpMV Multiplication
R Chinthala, A Datta, SK Nandy
13th Australasian Symposium on Parallel and Distributed Computing, 93-96, 2015
2015
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Articles 1–17