Follow
SUNNY ANAND
SUNNY ANAND
HCl, Noida
Verified email at hcltech.com
Title
Cited by
Cited by
Year
Design and performance analysis of dielectrically modulated doping-less tunnel FET-based label free biosensor
S Anand, A Singh, SI Amin, AS Thool
IEEE Sensors Journal 19 (12), 4369-4374, 2019
1092019
Analog performance investigation of dual electrode based doping-less tunnel FET
S Anand, SI Amin, RK Sarin
Journal of Computational Electronics 15, 94-103, 2016
902016
Design and Performance Analysis of Tunnel Field Effect Transistor With Buried Strained Si1−xGex Source Structure Based Biosensor for Sensitivity Enhancement
A Anam, S Anand, SI Amin
IEEE Sensors Journal 20 (22), 13178-13185, 2020
832020
Design and performance analysis of dual-gate all around core-shell nanotube TFET
N Kumar, U Mushtaq, SI Amin, S Anand
Superlattices and Microstructures 125, 356-364, 2019
642019
Design and Performance Optimization of Novel Core–Shell Dopingless GAA-Nanotube TFET With Si0.5Ge0.5-Based Source
N Kumar, SI Amin, S Anand
IEEE Transactions on Electron Devices 67 (3), 789-795, 2020
612020
Design of Si0. 5Ge0. 5 based tunnel field effect transistor and its performance evaluation
G Singh, SI Amin, S Anand, RK Sarin
Superlattices and Microstructures 92, 143-156, 2016
612016
Core-shell junctionless nanotube tunnel field effect transistor: Design and sensitivity analysis for biosensing application
S Shreya, AH Khan, N Kumar, SI Amin, S Anand
IEEE Sensors Journal 20 (2), 672-679, 2019
592019
Performance analysis of charge plasma based dual electrode tunnel FET
S Anand, SI Amin, RK Sarin
Journal of Semiconductors 37 (5), 054003, 2016
442016
An analysis on ambipolar reduction techniques for charge plasma based tunnel field effect transistors
S Anand, RK Sarin
Journal of Nanoelectronics and Optoelectronics 11 (4), 543-550, 2016
382016
Analog and RF performance of doping-less tunnel FETs with source
S Anand, RK Sarin
Journal of Computational Electronics 15, 850-856, 2016
312016
Design and performance optimization of dopingless vertical nanowire TFET using gate stacking technique
A Bhardwaj, P Kumar, B Raj, S Anand
Journal of Electronic Materials 51 (7), 4005-4013, 2022
302022
Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance
S Anand, RK Sarin
Journal of Semiconductors 38 (2), 024001, 2017
292017
Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform
S Anand, RK Sarin
Superlattices and Microstructures 97, 60-69, 2016
272016
Effect of Varying Glucose Concentrations during In Vitro Maturation and Embryo Culture on Efficiency of In Vitro Embryo Production in Buffalo
P Kumar, A Verma, B Roy, S Rajput, S Ojha, S Anand, P Yadav, J Arora, ...
Reproduction in domestic animals 47 (2), 269-273, 2012
242012
Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation
A Anam, SI Amin, D Prasad, N Kumar, S Anand
Physica Scripta 98 (9), 095918, 2023
192023
Charge-plasma based symmetrical-gate complementary electron–hole bilayer TFET with improved performance for sub-0.5 V operation
A Anam, N Kumar, SI Amin, D Prasad, S Anand
Semiconductor Science and Technology 38 (1), 015012, 2022
192022
Label free detection of biomolecules using SiGe sourced dual electrode doping-less dielectrically modulated tunnel FET
A Singh, SI Amin, S Anand
Silicon 12, 2301-2308, 2020
192020
Analysis of dielectrically modulated doping-less transistor for biomolecule detection using the charge plasma technique
SI Amin, L Gajal, S Anand
Applied Physics A 124, 1-8, 2018
192018
Implementation of negative capacitance over SiGe sourced Doping-less Tunnel FET
A Singh, N Kumar, SI Amin, S Anand
Superlattices and Microstructures 145, 106580, 2020
172020
Gate misalignment effects on analog/RF performance of charge plasma-based doping-less tunnel FET
S Anand, RK Sarin
Applied Physics A 123, 1-10, 2017
172017
The system can't perform the operation now. Try again later.
Articles 1–20