| Physically tightly coupled, logically loosely coupled, near-memory BNN accelerator (PTLL-BNN) YC Lo, YC Kuo, YS Chang, JH Huang, JS Wu, WC Ting, TH Wen, RS Liu ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 8 | 2019 |
| ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators YC Lo, CC Yeh, JS Wu, CC Wang, YC Tsai, WC Ting, RS Liu Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 5 | 2022 |
| Value-aware error detection and correction for SRAM buffers in low-bitwidth, floating-point CNN accelerators JS Wu, CE Wang, RS Liu Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 3 | 2021 |
| SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs JS Wu, TW Hsu, RS Liu ACM Transactions on Embedded Computing Systems 22 (6), 1-22, 2023 | 2 | 2023 |
| Processor for neural network operation LO Yun-Chen, KUO Yu-Chun, YS CHANG, JH HUANG, WU Jun-Shen, ... US Patent App. 17/108,470, 2021 | 2 | 2021 |
| ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory YC Lo, JS Wu, CC Wang, YC Tsai, CC Yeh, WC Ting, RS Liu IEEE Transactions on Computers, 2024 | | 2024 |
| Memory device WU Jun-Shen, W Chi-En, RS Liu US Patent 11,947,828, 2024 | | 2024 |
| Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators CC Wang, YC Lo, JS Wu, YC Tsai, CC Chang, TW Hsu, MW Chu, CY Lai, ... 2023 IEEE 41st International Conference on Computer Design (ICCD), 515-522, 2023 | | 2023 |
| FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators JS Wu, RS Liu 2023 IEEE 41st International Conference on Computer Design (ICCD), 407-414, 2023 | | 2023 |
| Floating-point calculation method and associated arithmetic unit WU Jun-Shen, RS Liu US Patent App. 18/104,311, 2023 | | 2023 |
