| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 344 | 2020 |
| Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling S Bharadwaj, J Yin, B Beckmann, T Krishna 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 83* | 2020 |
| Scalable distributed last-level tlbs using low-latency interconnects S Bharadwaj, G Cox, T Krishna, A Bhattacharjee 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 27 | 2018 |
| Network-on-chip security and privacy P Mishra, S Charles Springer International Publishing, 2021 | 24 | 2021 |
| Accelerating variational quantum algorithms using circuit concurrency S Resch, A Gutierrez, JS Huh, S Bharadwaj, Y Eckert, G Loh, M Oskin, ... arXiv preprint arXiv:2109.01714, 2021 | 14 | 2021 |
| Optimizing GPU cache policies for MI workloads J Alsop, MD Sinclair, S Bharadwaj, A Dutu, A Gutierrez, O Kayiran, ... 2019 IEEE International Symposium on Workload Characterization (IISWC), 243-248, 2019 | 14 | 2019 |
| Dub: Dynamic underclocking and bypassing in NoCs for heterogeneous GPU workloads. In 2021 15th IEEE S Bharadwaj, S Das, Y Eckert, M Oskin, T Krishna ACM International Symposium on Networks-on-Chip (NOCS), 49-54, 2021 | 11* | 2021 |
| Predict; don't react for enabling efficient fine-grain dvfs in gpus S Bharadwaj, S Das, K Mazumdar, BM Beckmann, S Kosonocky Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 10 | 2023 |
| Credit based flow control mechanism for use in multiple link width interconnect systems S Bharadwaj US Patent 10,671,554, 2020 | 6 | 2020 |
| Packet router with virtual channel hop buffer control VVS Bharadwaj US Patent 11,398,980, 2022 | 3 | 2022 |
| Quantum circuit mapping for multi-programmed quantum computers AT Gutierrez, S Resch, Y Eckert, GH Loh, MH Oskin, VVS Bharadwaj US Patent 11,922,107, 2024 | 2 | 2024 |
| Interconnect Modeling for Homogeneous and Heterogeneous Multiprocessors T Krishna, S Bharadwaj Network-on-Chip Security and Privacy, 31-54, 2021 | 2 | 2021 |
| Dynamically configurable overprovisioned microprocessor A Gutierrez, VVS Bharadwaj, Y Eckert, MH Oskin US Patent 11,989,591, 2024 | 1 | 2024 |
| Chiplet-level performance information for configuring chiplets in a processor S Ganapathy, Y Eckert, A Gutierrez, KR Sangaiah, VVS Bharadwaj US Patent 11,797,410, 2023 | 1 | 2023 |
| Routing flits in a network-on-chip based on operating states of routers S Bharadwaj, SN Das US Patent 10,944,693, 2021 | 1 | 2021 |
| Semiconductor device for performing data reduction for processing arrays WP Ehrett, A Gutierrez, VVS Bharadwaj, KR Sangaiah, P Shukla, ... US Patent App. 18/217,079, 2025 | | 2025 |
| TURBOATTENTION: Efficient Attention Approximation For High Throughputs LLMs H Kang, S Bharadwaj, J Hensman, T Krishna, V Ruhle, S Rajmohan arXiv preprint arXiv:2412.08585, 2024 | | 2024 |
| InC2: Design of Interconnection Systems for Composable Chiplet Architectures S Bharadwaj, T Krishna 2024 17th IEEE/ACM International Workshop on Network on Chip Architectures …, 2024 | | 2024 |
| Dynamic voltage frequency scaling based on active memory barriers VVS Bharadwaj US Patent 12,124,311, 2024 | | 2024 |
| Distribution of data and memory timing parameters across memory modules based on memory access patterns M Ruttenberg, VVS Bharadwaj, Y Eckert, A Gutierrez, MH Oskin US Patent 12,079,145, 2024 | | 2024 |
Anthony GutierrezAMD Research and Advanced DevelopmentVerified email at amd.com
