| Design of testable reversible sequential circuits H Thapliyal, N Ranganathan, S Kotiyal IEEE transactions on very large scale integration (VLSI) systems 21 (7 …, 2012 | 196 | 2012 |
| Mach-Zehnder interferometer based design of all optical reversible binary adder S Kotiyal, H Thapliyal, N Ranganathan 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 721-726, 2012 | 101 | 2012 |
| Novel BCD adders and their reversible logic implementation for IEEE 754r format H Thapliyal, S Kotiyal, MB Srinivas 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 98 | 2006 |
| Circuit for reversible quantum multiplier based on binary tree optimizing ancilla and garbage bits S Kotiyal, H Thapliyal, N Ranganathan 2014 27th international conference on VLSI design and 2014 13th …, 2014 | 69 | 2014 |
| Mach-Zehnder interferometer based all optical reversible NOR gates S Kotiyal, H Thapliyal, N Ranganathan 2012 IEEE Computer Society Annual Symposium on VLSI, 207-212, 2012 | 64 | 2012 |
| Design and analysis of a novel parallel square and cube architecture based on ancient Indian Vedic mathematics H Thapliyal, S Kotiyal, MB Srinivas 48th Midwest Symposium on Circuits and Systems, 2005., 1462-1465, 2005 | 64 | 2005 |
| Design of a ternary barrel shifter using multiple-valued reversible logic S Kotiyal, H Thapliyal, N Ranganathan 10th IEEE international conference on Nanotechnology, 1104-1108, 2010 | 55 | 2010 |
| Design of a reversible bidirectional barrel shifter S Kotiyal, H Thapliyal, N Ranganathan 2011 11th IEEE International Conference on Nanotechnology, 463-468, 2011 | 52 | 2011 |
| Reversible logic based multiplication computing unit using binary tree data structure S Kotiyal, H Thapliyal, N Ranganathan The Journal of Supercomputing 71 (7), 2668-2693, 2015 | 28 | 2015 |
| Efficient reversible NOR gates and their mapping in optical computing domain S Kotiyal, H Thapliyal, N Ranganathan Microelectronics Journal 45 (6), 825-834, 2014 | 19 | 2014 |
| Reversible logic based design and test of field coupled nanocomputing circuits H Thapliyal, N Ranganathan, S Kotiyal Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives, 133-172, 2014 | 18 | 2014 |
| Design methodologies for reversible logic based barrel shifters S Kotiyal, H Thapliyal Journal of Circuits, Systems and Computers 25 (02), 1650003, 2016 | 12 | 2016 |
| Design exploration and application of reversible circuits in emerging technologies S Kotiyal University of South Florida, 2016 | 4 | 2016 |
| Design of reversible adder-subtractor and its mapping in optical computing domain S Kotiyal, H Thapliyal, N Ranganathan transactions on Computational Science XXIV: Special Issue on Reversible …, 2014 | 2 | 2014 |
| A new weather warning tool that incorporates census data J Collins, CH Paxton, TL Hansen, JL Simms, K Hirvela, S Kotiyal AGU Fall Meeting Abstracts, 2011 | | 2011 |
| Designing a Grätzel Cell R Hyman Jr, S Kotiyal | | 2010 |
| High Speed Hardware Units for Efficient Performance of Modified Montgomery Multiplication H Thapliyal, S Kotiyal, MB Srinivas 8th International Conference on Information Technology (CIT-2005), 2005 | | 2005 |
| Reversible Logic Design of 4: 2 and 5: 2 and Higher Order Compressors H Thapliyal, S Kotiyal, MB Srinivas 대한전자공학회 ISOCC, 504-507, 2005 | | 2005 |
| VLSI Implementation of O(n*n) Sorting Algorithms and their Hardware Comparison S Kotiyal, H Thapliyal, MB Srinivas, HR Arabnia 2005 International Conference on Scientific Computing, 74-77, 2005 | | 2005 |
| ISVLSI 2013 Additional Reviewers A Gamatie, A Makosiej, A Habashi, A Jerraya, A Sammod, A Todri, ... | | |