| Analysis and mitigation of interface losses in trenched superconducting coplanar waveguide resonators G Calusine, A Melville, W Woods, R Das, C Stull, V Bolkhovsky, D Braje, ... Applied Physics Letters 112 (6), 2018 | 152 | 2018 |
| Determining interface dielectric losses in superconducting coplanar-waveguide resonators W Woods, G Calusine, A Melville, A Sevi, E Golden, DK Kim, ... Physical Review Applied 12 (1), 014012, 2019 | 142 | 2019 |
| Solid-state qubits integrated with superconducting through-silicon vias DRW Yost, ME Schwartz, J Mallek, D Rosenberg, C Stull, JL Yoder, ... npj Quantum Information 6 (1), 59, 2020 | 120 | 2020 |
| CMOS millimeter wave phase shifter based on tunable transmission lines WH Woods, A Valdes-Garcia, H Ding, J Rascoe Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 71 | 2013 |
| Comparison of dielectric loss in titanium nitride and aluminum superconducting resonators A Melville, G Calusine, W Woods, K Serniak, E Golden, BM Niedzielski, ... Applied Physics Letters 117 (12), 2020 | 68 | 2020 |
| Solid-state qubits: 3D integration and packaging D Rosenberg, SJ Weber, D Conway, DRW Yost, J Mallek, G Calusine, ... IEEE Microwave Magazine 21 (8), 72-85, 2020 | 60 | 2020 |
| A 18mw, 3.3 db nf, 60ghz lna in 32nm soi cmos technology with autonomic nf calibration JO Plouchart, F Wang, A Balteanu, B Parker, MAT Sanduleanu, M Yeck, ... 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 319-322, 2015 | 34 | 2015 |
| A new on-wafer de-embedding technique for on-chip RF transmission line interconnect characterization Y Tretiakov, K Vaed, W Woods, S Venkatadri, T Zwick ARFTG 63rd Conference, Spring 2004, 69-72, 2004 | 34 | 2004 |
| On-chip integrated voltage-controlled variable inductor, methods of making and tuning such variable inductors, and design structures integrating such variable inductors H Ding, EF Mina, WH Woods US Patent 8,138,876, 2012 | 32 | 2012 |
| Bias-controlled deep trench substrate noise isolation integrated circuit device structures PF Chapman, D Goren, R Krishnasamy, B Sheinman, S Shlafman, ... US Patent 8,021,941, 2011 | 31 | 2011 |
| Neural-network-based parasitic modeling and extraction verification for RF/millimeter-wave integrated circuit design P Sen, WH Woods, S Sarkar, RJ Pratap, BM Dufrene, R Mukhopadhyay, ... IEEE Transactions on Microwave theory and Techniques 54 (6), 2604-2614, 2006 | 30 | 2006 |
| Push-pop memory stack having reach down mode and improved means for processing double-word items W Woods US Patent 3,786,432, 1974 | 28 | 1974 |
| Fabrication of superconducting through-silicon vias JL Mallek, DRW Yost, D Rosenberg, JL Yoder, G Calusine, M Cook, ... arXiv preprint arXiv:2103.08536, 2021 | 27 | 2021 |
| Microwave packaging for superconducting qubits B Lienhard, J Braumüller, W Woods, D Rosenberg, G Calusine, S Weber, ... 2019 IEEE MTT-S International Microwave Symposium (IMS), 275-278, 2019 | 27 | 2019 |
| Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance H Ding, WH Woods Jr US Patent 8,193,878, 2012 | 23 | 2012 |
| On wafer de-embedding for SiGe/BiCMOS/RFCMOS transmission line interconnect characterization Y Tretiakov, K Vaed, D Ahlgren, J Rascoe, S Venkatadri, W Woods Proceedings of the IEEE 2004 International Interconnect Technology …, 2004 | 22 | 2004 |
| Methods of fabricating coplanar waveguide structures H Ding, EF Mina, G Wang, WH Woods US Patent 8,028,406, 2011 | 21 | 2011 |
| Tunable interconnect structures, and integrated circuit containing the same DC Edelstein, A Valdes-Garcia, SM Gates, WH Woods Jr US Patent 9,059,679, 2015 | 19 | 2015 |
| Generating an electromagnetic parameterized cell for an integrated circuit design SE Strang, HH Tran, WH Woods Jr, Z Zhang US Patent App. 14/533,148, 2016 | 18 | 2016 |
| Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance H Ding, WH Woods Jr US Patent 8,138,857, 2012 | 18 | 2012 |
