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Thomas Haine
Thomas Haine
E-peas S.A., formerly ICTEAM Institute, Université catholique de Louvain
Verified email at e-peas.com
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Cited by
Cited by
Year
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW …
D Bol, M Schramme, L Moreau, P Xu, R Dekimpe, R Saeidi, T Haine, ...
IEEE Journal of Solid-State Circuits 56 (7), 2256-2269, 2021
362021
19.6 A 40-to-80MHz Sub-4μw/mhz ULV cortex-M0 MCU SoC in 28nm FDSOI with dual-loop adaptive back-bias generator for 20μs wake-up from deep fully retentive sleep mode
D Bol, M Schramme, L Moreau, T Haine, P Xu, C Frenkel, R Dekimpe, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 322-324, 2019
362019
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics
T Haine, J Segers, D Flandre, D Bol
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 195-200, 2018
232018
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation
T Haine, QK Nguyen, F Stas, L Moreau, D Flandre, D Bol
ESSCIRC 2017- 43rd IEEE European Solid State Circuits Conference, pp. 312-315, 2017
142017
8-T ULV SRAM macro in 28nm FDSOI with 7.4 pW/bit retention power and back-biased-scalable speed/energy trade-off
T Haine, D Flandre, D Bol
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
52018
CAMEL: An ultra-low-power VGA CMOS imager based on a time-based DPS array
T Haine, F Stas, G de Streel, C Gimeno, D Flandre, D Bol
Proceedings of the 10th International Conference on Distributed Smart Camera …, 2016
22016
Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes
T Haine, F Stas, D Bol
2014 IEEE Faible Tension Faible Consommation, 2014
22014
Analysis and optimization for dynamic read stability in 28nm SRAM bitcells
AT Elthakeb, T Haine, D Flandre, Y Ismail, H Abd Elhamid, D Bol
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1414-1417, 2015
12015
Large array-based circuits in ULV SoCs : design and statistical assessment of SRAMs and CMOS imagers
T Haine
Université catholique de Louvain, 2018
2018
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