| Design of adder and subtractor circuits in majority logic‐based field‐coupled QCA nanocomputing C Labrado, H Thapliyal Electronics letters 52 (6), 464-466, 2016 | 139 | 2016 |
| Stress detection and management: A survey of wearable smart health devices H Thapliyal, V Khalus, C Labrado IEEE Consumer Electronics Magazine 6 (4), 64-69, 2017 | 106 | 2017 |
| Design of a piezoelectric-based physically unclonable function for IoT security C Labrado, H Thapliyal IEEE Internet of Things Journal 6 (2), 2770-2777, 2018 | 41 | 2018 |
| Use of thermistor temperature sensors for cyber-physical system security C Labrado, H Thapliyal, S Prowell, T Kuruganti Sensors 19 (18), 3905, 2019 | 36 | 2019 |
| Design of majority logic based approximate arithmetic circuits C Labrado, H Thapliyal, F Lombardi 2017 IEEE international symposium on circuits and systems (ISCAS), 1-4, 2017 | 34 | 2017 |
| Hardware security primitives for vehicles C Labrado, H Thapliyal IEEE Consumer Electronics Magazine 8 (6), 99-103, 2019 | 23 | 2019 |
| Fortifying vehicular security through low overhead physically unclonable functions C Labrado, H Thapliyal, SP Mohanty ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-18, 2021 | 14 | 2021 |
| Amazon echo enabled iot home security system for smart home environment H Thapliyal, N Ratajczak, O Wendroth, C Labrado 2018 IEEE International Symposium on Smart Electronic Systems (iSES …, 2018 | 12 | 2018 |
| Solar cell based physically unclonable function for cybersecurity in IoT devices SD Kumar, C Labrado, R Badhan, H Thapliyal, V Singh 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 697-702, 2018 | 11 | 2018 |
| A puf based can security framework T Cultice, C Labrado, H Thapliyal 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 602-603, 2020 | 7 | 2020 |
| Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing C Labrado, H Thapliyal Electronics Letters 52 (19), 1618-1620, 2016 | 5 | 2016 |
| Exploration of majority logic based designs for arithmetic circuits C Labrado | 4 | 2017 |
| Exploration of solar cell materials for developing novel pufs in cyber-physical systems C Labrado, SD Kumar, R Badhan, H Thapliyal, V Singh SN Computer Science 1, 1-13, 2020 | 3 | 2020 |
| Design of testable adder circuits for spintronics based nanomagnetic computing C Labrado, H Thapliyal, RF Demara 2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015 | 3 | 2015 |
| Energy harvesting and sensor based hardware security primitives for cyber-physical systems C Labrado | 2 | 2021 |
| Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines H Thapliyal, C Labrado, K Chen The Journal of Supercomputing 72, 1092-1124, 2016 | 2 | 2016 |
| Architecture for generating physically unclonable function response H Thapliyal, C Labrado US Patent 11,206,146, 2021 | 1 | 2021 |
| Aatreyi Bal Abhranil Maiti Andrea Calimera Ao Ren A Roohi, A Yasin, A Bose, A Aysu, AF Tabrizi, B Behazin, B Liang, B Li, ... | | |
| ISVLSI 2017 Additional Reviewers A Srivastava, A Singh, A Ilic, A Barteau, A Dantas, B Ege, ... | | |
