| Towards a uniform template-based architecture for accelerating 2D and 3D CNNs on FPGA J Shen, Y Huang, Z Wang, Y Qiao, M Wen, C Zhang Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 120 | 2018 |
| FPGA‐accelerated deep convolutional neural networks for high throughput and energy efficiency Y Qiao, J Shen, T Xiao, Q Yang, M Wen, C Zhang Concurrency and Computation: Practice and Experience 29 (20), e3850, 2017 | 75 | 2017 |
| Toward an efficient deep pipelined template-based architecture for accelerating the entire 2-D and 3-D CNNs on FPGA J Shen, Y Huang, M Wen, C Zhang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 42 | 2019 |
| Towards a multi-array architecture for accelerating large-scale matrix multiplication on FPGAs J Shen, Y Qiao, Y Huang, M Wen, C Zhang 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 32 | 2018 |
| A high-efficiency FPGA-based accelerator for convolutional neural networks using Winograd algorithm Y Huang, J Shen, Z Wang, M Wen, C Zhang Journal of Physics: Conference Series 1026 (1), 012019, 2018 | 27 | 2018 |
| P4 to FPGA-a fast approach for generating efficient network processors Z Cao, H Su, Q Yang, J Shen, M Wen, C Zhang IEEE Access 8, 23440-23456, 2020 | 21 | 2020 |
| Scale-out acceleration for 3D CNN-based lung nodule segmentation on a multi-FPGA system J Shen, D Wang, Y Huang, M Wen, C Zhang Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 19 | 2019 |
| Efficient implementation of 2D and 3D sparse deconvolutional neural networks with a uniform architecture on FPGAs D Wang, J Shen, M Wen, C Zhang Electronics 8 (7), 803, 2019 | 12 | 2019 |
| Towards a uniform architecture for the efficient implementation of 2D and 3D deconvolutional neural networks on FPGAs D Wang, J Shen, M Wen, C Zhang 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 12 | 2019 |
| Towards memory-efficient streaming processing with counter-cascading sketching on FPGA M Tang, M Wen, J Shen, X Zhao, C Zhang 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 10 | 2020 |
| MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA Y Huang, J Shen, Y Qiao, M Wen, C Zhang IEICE Electronics Express 15 (10), 20180286-20180286, 2018 | 8 | 2018 |
| Mentha: Enabling Sparse-Packing Computation on Systolic Arrays M Tang, M Wen, Y Cao, J Shen, J Yang, J Fei, Y Guo, S Liu Proceedings of the 51st International Conference on Parallel Processing, 1-11, 2022 | 7 | 2022 |
| BP-im2col: Implicit im2col supporting AI backpropagation on systolic arrays J Yang, M Wen, J Shen, Y Cao, M Tang, R Yang, J Fei, C Zhang 2022 IEEE 40th International Conference on Computer Design (ICCD), 415-418, 2022 | 5 | 2022 |
| An efficient design flow for accelerating complicated-connected CNNs on a multi-FPGA platform D Wang, J Shen, M Wen, C Zhang Proceedings of the 48th International Conference on Parallel Processing, 1-10, 2019 | 5 | 2019 |
| Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. J Shen, D Wang, Y Huang, M Wen, C Zhang FPGA, 117, 2019 | 4 | 2019 |
| Optimizing opencl implementation of deep convolutional neural network on FPGA Y Qiao, J Shen, D Huang, Q Yang, M Wen, C Zhang Network and Parallel Computing: 14th IFIP WG 10.3 International Conference …, 2017 | 4 | 2017 |
| Unified virtual memory support for deep CNN accelerator on SoC FPGA T Xiao, Y Qiao, J Shen, Q Yang, M Wen Algorithms and Architectures for Parallel Processing: 15th International …, 2015 | 4 | 2015 |
| MZ Core: An Enhanced Matrix Acceleration Engine for HPC/AI Applications Y Cao, M Wen, J Shen, S Liu, Z Wang, M Tang, Y Fang, J Yang, R Yang, ... 2022 IEEE 24th Int Conf on High Performance Computing & Communications; 8th …, 2022 | 3 | 2022 |
| Towards a deep-pipelined architecture for accelerating deep GCN on a multi-FPGA platform Q Cheng, M Wen, J Shen, D Wang, C Zhang International Conference on Algorithms and Architectures for Parallel …, 2020 | 3 | 2020 |
| S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness Y Li, M Wen, R Yang, J Shen, Y Cao, J Wang 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2720-2724, 2022 | 2 | 2022 |
Xing CaiProfessor at University of Oslo, Chief Research Scientist at Simula Research LaboratoryVerified email at simula.no