| High level synthesis of ASICs under timing and synchronization constraints DC Ku, G DeMicheli Springer Science & Business Media, 2013 | 230 | 2013 |
| The Olympus synthesis system G De Micheli, D Ku, F Mailhot, T Truong IEEE Design & Test of Computers 7 (5), 37-53, 1990 | 196 | 1990 |
| Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits DC Ku, G De Mitcheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1992 | 150 | 1992 |
| Hardware C-a language for hardware design DC Ku, G De Micheli Computer Systems Laboratory, Stanford University, 1988 | 143 | 1988 |
| HERCULES-a System for High-Level Synthesis. G De Micheli, DC Ku DAC, 483-488, 1988 | 133 | 1988 |
| HardwareC-A Language for Hardware Design, Version 2.0 D Ku, G De Micheli Computer Systems Laboratory, Stanford University, 1990 | 128 | 1990 |
| Relative scheduling under timing constraints D Ku, G De Micheli Proceedings of the 27th ACM/IEEE Design Automation Conference, 59-64, 1991 | 98 | 1991 |
| Interface optimization for concurrent systems under timing constraints D Filo, DC Ku, CN Coelho, G De Micheli IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (3), 268-281, 1993 | 87 | 1993 |
| High-level synthesis and optimization strategies in Hercules and Hebe D Ku, G De Micheli [Proceedings] EURO ASIC90, 124-129, 1990 | 37 | 1990 |
| Optimal synthesis of control logic from behavioral specifications DC Ku, G De Micheli Integration 10 (3), 271-298, 1991 | 24 | 1991 |
| Constrained resource sharing and conflict resolution in Hebe DC Ku, G De Micheli Integration 12 (2), 131-165, 1991 | 22 | 1991 |
| Optimizing the control-unit through the resynchronization of operations D Filo, DC Ku, G De Micheli Integration 13 (3), 231-258, 1992 | 20 | 1992 |
| Constrained synthesis and optimization of digital integrated circuits from behavioral specifications DCL Ku Stanford University, 1991 | 18 | 1991 |
| Synthesis of asics with hercules and hebe DC Ku, G De Micheli High-level VLSI synthesis, 177-203, 1991 | 16 | 1991 |
| Control optimization based on resynchronization of operations DC Ku, D Filo, G De Micheli Proceedings of the 28th ACM/IEEE Design Automation Conference, 366-371, 1991 | 13 | 1991 |
| SYNTHESIS SYSTEM D KU | 10 | 1988 |
| Gionvanni De Micheli, Relative scheduling under timing constraints D Ku Proceedings of the 27 thACM/IEEE conference on Design automation, 59-64, 1990 | 7 | 1990 |
| High-Level Synthesis K Tu, X Tang, C Yu, L Josipović, Z Chu FPGA EDA: Design Principles and Implementation, 113-134, 2024 | 3 | 2024 |
| Design space exploration DC Ku, G De Micheli, DC Ku, G De Micheli High Level Synthesis of ASICs under Timing and Synchronization Constraints …, 1992 | 1 | 1992 |
| Intranets and EDA: impact, application, and technology D Ku, J Rowson Proceedings of the 1996 IEEE/ACM international conference on Computer-aided …, 1997 | | 1997 |
