| NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark A Lu, X Peng, W Li, H Jiang, S Yu Frontiers in Artificial Intelligence, 2021 | 51 | 2021 |
| Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators H Jiang, W Li, S Huang, S Cosemans, F Catthoor, S Yu IEEE Design & Test, 2021 | 49 | 2021 |
| A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References W Li, X Sun, S Huang, H Jiang, S Yu IEEE Journal of Solid-State Circuits (JSSC), 2022 | 44 | 2022 |
| A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays H Jiang, W Li, S Huang, S Yu IEEE Symposium on VLSI Technology and Circuits (VLSI), 2022 | 43 | 2022 |
| Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security W Li, S Huang, X Sun, H Jiang, S Yu IEEE Custom Integrated Circuits Conference (CICC), 2021 | 33 | 2021 |
| XOR-CIM: Compute-in-Memory SRAM Architecture with Embedded XOR Encryption S Huang, H Jiang, X Peng, W Li, S Yu IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020 | 31 | 2020 |
| A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References W Li, X Sun, H Jiang, S Huang, S Yu IEEE European Solid State Circuits Conference (ESSCIRC), 2021 | 25 | 2021 |
| NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro A Lu, X Peng, W Li, H Jiang, S Yu IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021 | 23 | 2021 |
| Secure XOR-CIM Engine: Compute-in-Memory SRAM Architecture With Embedded XOR Encryption S Huang, H Jiang, X Peng, W Li, S Yu IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2021 | 14 | 2021 |
| Compute-in-Memory: From Device Innovation to 3D System Integration S Yu, W Shim, J Hur, Y Luo, G Choe, W Li, A Lu, X Peng IEEE European Solid-State Device Research Conference (ESSDERC), 2021 | 13 | 2021 |
| H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention W Li, M Manley, J Read, A Kaul, MS Bakir, S Yu IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2023 | 12 | 2023 |
| ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays H Jiang, S Huang, W Li, S Yu IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2022 | 11 | 2022 |
| A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling W Li, J Read, H Jiang, S Yu IEEE European Solid State Circuits Conference (ESSCIRC), 2022 | 8 | 2022 |
| RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers W Li, Y Luo, S Yu IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023 | 6 | 2023 |
| MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine W Li, J Read, H Jiang, S Yu IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2022 | 6 | 2022 |
| A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators J Read, W Li, S Yu IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022 | 6 | 2022 |
| NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node J Lee, A Lu, W Li, S Yu IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2024 | 5 | 2024 |
| Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute J Sharda, W Li, Q Wu, S Chang, S Yu IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2023 | 5 | 2023 |
| Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving W Li, Q Wu, J Sharda, S Chang, S Yu IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022 | 5 | 2022 |
| Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array W Li, J Lee, S Yu IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023 | 4 | 2023 |
Shimeng YuGeorgia Institute of Technology, Dean's ProfessorVerified email at ece.gatech.edu