| Optimal synthesis of multiple output boolean functions using a set of quantum gates by symbolic reachability analysis WNN Hung, X Song, G Yang, J Yang, M Perkowski IEEE transactions on Computer-Aided Design of integrated circuits and …, 2006 | 325 | 2006 |
| Backspace: Formal analysis for post-silicon debug FM De Paula, M Gort, AJ Hu, SJE Wilton, J Yang 2008 Formal Methods in Computer-Aided Design, 1-10, 2008 | 110 | 2008 |
| Quantum logic synthesis by symbolic reachability analysis WNN Hung, X Song, G Yang, J Yang, M Perkowski Proceedings of the 41st annual Design Automation Conference, 838-841, 2004 | 106 | 2004 |
| Introduction to generalized symbolic trajectory evaluation J Yang, CJH Seger IEEE transactions on very large scale integration (VLSI) systems 11 (3), 345-353, 2003 | 95 | 2003 |
| Generalized symbolic trajectory evaluation—abstraction in action J Yang, CJH Seger Formal Methods in Computer-Aided Design: 4th International Conference, FMCAD …, 2002 | 63 | 2002 |
| Security of SoC firmware load protocols S Krstić, J Yang, DW Palmer, RB Osborne, E Talmor 2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014 | 49 | 2014 |
| Symbolic model checking for event-driven real-time systems J Yang, AK Mok, F Wang ACM Transactions on Programming Languages and Systems (TOPLAS) 19 (2), 386-412, 1997 | 43 | 1997 |
| Optimizing equivalence checking for behavioral synthesis K Hao, F Xie, S Ray, J Yang 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 41 | 2010 |
| Efficient generation of monitor circuits for GSTE assertion graphs AJ Hu, J Cases, J Yang ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 38 | 2003 |
| Correctness and security at odds: Post-silicon validation of modern SoC designs S Ray, J Yang, A Basak, S Bhunia Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 37 | 2015 |
| Formal verification for high-assurance behavioral synthesis S Ray, K Hao, Y Chen, F Xie, J Yang Automated Technology for Verification and Analysis: 7th International …, 2009 | 30 | 2009 |
| GSTE through a case study J Yang, A Goel Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 29 | 2002 |
| GSTE through a case study J Yang, A Goel Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 29 | 2002 |
| Symbolic model checking for event-driven real-time systems J Yang, A Mok, F Wang 1993 Proceedings Real-Time Systems Symposium, 23-32, 1993 | 27 | 1993 |
| Generalized symbolic trajectory evaluation J Yang, CJ Seger STE Symposium, A Satellite Workshop of CAV’2000, 2000 | 26 | 2000 |
| Reasoning about GSTE assertion graphs AJ Hu, J Casas, J Yang Advanced Research Working Conference on Correct Hardware Design and …, 2003 | 23 | 2003 |
| Symbolic variable reduction J Yang US Patent 6,591,400, 2003 | 20 | 2003 |
| Mining Message Flows from System-on-Chip Execution Traces MR Ahmed, H Zheng, P Mukherjee, MC Ketkar, J Yang 2021 22nd International Symposium on Quality Electronic Design (ISQED), 374-380, 2021 | 15 | 2021 |
| UEFI firmware fuzzing with simics virtual platform Z Yang, Y Viktorov, J Yang, J Yao, V Zimmer 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 13 | 2020 |
| Formal-analysis-based trace computation for post-silicon debug M Gort, FM De Paula, JJW Kuan, TM Aamodt, AJ Hu, SJE Wilton, J Yang IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011 | 13 | 2011 |
Guowu Yang （杨国武）电子科技大学Verified email at uestc.edu.cn