| Fault-tolerant nanoscale processors on semiconductor nanowire grids CA Moritz, T Wang, P Narayanan, M Leuchtenburg, Y Guo, C Dezan, ... IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2422-2437, 2007 | 84 | 2007 |
| Opportunities and challenges in application-tuned circuits and architectures based on nanodevices T Wang, Z Qi, CA Moritz Proceedings of the 1st conference on Computing frontiers, 503-511, 2004 | 57 | 2004 |
| CMOS control enabled single-type FET NASIC P Narayanan, M Leuchtenburg, T Wang, CA Moritz 2008 IEEE Computer Society Annual Symposium on VLSI, 191-196, 2008 | 52 | 2008 |
| Latching on the wire and pipelining in nanoscale designs CA Moritz, T Wang Non-Silicon Computing Workshop, NSC 3, 2004 | 44 | 2004 |
| Heterogeneous Two-Level logic and its density and fault tolerance implications in nanoscale fabrics T Wang, P Narayanan, CA Moritz IEEE Transactions on Nanotechnology 8 (1), 22-30, 2008 | 40 | 2008 |
| Wire-streaming processors on 2-D nanowire fabrics T Wang, M Ben-Naser, Y Guo, CA Moritz NSTI (Nano Science and Technology Institute) Nanotech 5, 2005 | 38 | 2005 |
| Towards defect-tolerant nanoscale architectures CA Moritz, T Wang 2006 Sixth IEEE Conference on Nanotechnology 1, 331-334, 2006 | 29 | 2006 |
| NASICs: A nanoscale fabric for nanoscale microprocessors T Wang, P Narayanan, M Leuchtenburg, CA Moritz 2008 2nd IEEE International Nanoelectronics Conference, 989-994, 2008 | 26 | 2008 |
| Combining 2-level logic families in grid-based nanoscale fabrics T Wang, P Narayanan, CA Moritz 2007 IEEE International Symposium on Nanoscale Architectures, 101-108, 2007 | 26 | 2007 |
| Self-healing wire-streaming processors on 2-d semiconductor nanowire fabrics T Wang, M Bennaser, Y Guo, CA Moritz Proceedings of the NSTI (Nano Science and Technology Institute …, 2006 | 22 | 2006 |
| Image processing architecture for semiconductor nanowire based fabrics P Narayanan, T Wang, M Leuchtenburg, CA Moritz 2008 8th IEEE Conference on Nanotechnology, 677-680, 2008 | 19 | 2008 |
| Towards a framework for designing applications onto hybrid nano/CMOS fabrics C Dezan, C Teodorov, L Lagadec, M Leuchtenburg, T Wang, ... Microelectronics journal 40 (4-5), 656-664, 2009 | 13 | 2009 |
| Comparison of analog and digital nanosystems: Issues for the nano-architect P Narayanan, T Wang, M Leuchtenburg, CA Moritz 2008 2nd IEEE International Nanoelectronics Conference, 1003-1008, 2008 | 11 | 2008 |
| Combining circuit level and system level techniques for defect-tolerant nanoscale architectures T Wang, M Bennaser, Y Guo, CA Moritz Proceedings of the 2nd IEEE International Workshop on Defect and Fault …, 2006 | 11 | 2006 |
| Programmable cellular architectures at the nanoscale P Narayanan, T Wang, CA Moritz Nano Communication Networks 1 (2), 77-85, 2010 | 3 | 2010 |
| Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors M Leuchtenburg, P Narayanan, T Wang, CA Moritz International Conference on Nano-Networks, 26-27, 2008 | | 2008 |
Pritish NarayananIBM Research - AlmadenVerified email at us.ibm.com
