| A 7nm CMOS technology platform for mobile and high performance compute application S Narasimha, B Jagannathan, A Ogino, D Jaeger, B Greene, C Sheraw, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.5. 1-29.5. 4, 2017 | 72 | 2017 |
| III–V tunnel FET model with closed-form analytical solution JU Mehta, WA Borders, H Liu, R Pandey, S Datta, L Lunardi IEEE Transactions on Electron Devices 63 (5), 2163-2168, 2015 | 49 | 2015 |
| Lateral silicon photodiodes with extremely low dark current for visible and infra-red applications J Mehta, L Lunardi 2015 IEEE Photonics Conference (IPC), 446-447, 2015 | 3 | 2015 |
| A compact model for compound semiconductor tunneling field-effect-transistors JU Mehta, WA Borders, L Lunardi, H Liu, S Datta IEEE SOUTHEASTCON 2014, 1-3, 2014 | 1 | 2014 |
| LOW-RESISTANCE VIA STRUCTURES M Shen, C Choi, J Mehta, T Rahman, P Amin, JE Mueller, V Hipwell, ... US Patent App. 18/217,208, 2025 | | 2025 |
| Nanoribbon-based transistors with etch stop layer to assist subfin removal C Huang, G Xu, T Chu, R Chao, J Mehta, B Greene, CH Lin US Patent App. 18/174,007, 2024 | | 2024 |
| Device performance tuning by deep trench via (dvb) proximity effect in architecture of backside power delivery T Chu, M Jang, W Aurelia, CP Puls, L Hu, J Mehta, B Greene, CH Lin, ... US Patent App. 17/710,802, 2023 | | 2023 |
| Backside processing of fins in fin based transistor devices T Chu, M Jang, AC Wang, C Puls, B Greene, T Rahman, L Hu, J Mehta, ... US Patent App. 17/656,490, 2023 | | 2023 |
| Dummy fill scheme for use with passive devices J Mehta, B Greene, DJ Dechene, A Hassan US Patent 10,867,912, 2020 | | 2020 |
| Study and Fabrication of Lateral pin Photodiodes on Insulating Silicon Substrates JU Mehta North Carolina State University, 2016 | | 2016 |
