Follow
João Canas Ferreira
João Canas Ferreira
INESC TEC and University of Porto
Verified email at fe.up.pt - Homepage
Title
Cited by
Cited by
Year
An FPGA implementation of a long short-term memory neural network
JC Ferreira, J Fonseca
2016 International Conference on ReConFigurable Computing and FPGAs …, 2016
762016
Parallel implementation on FPGA of support vector machines using stochastic gradient descent
FF Lopes, JC Ferreira, MAC Fernandes
Electronics 8 (6), 631, 2019
402019
Control and observation of analog nodes in mixed-signal boards
JS Matos, AC Leao, JC Ferreira
Proceedings of IEEE International Test Conference-(ITC), 323-331, 1993
371993
Support for partial run-time reconfiguration of platform FPGAs
ML Silva, JC Ferreira
Journal of Systems Architecture 52 (12), 709-726, 2006
362006
Tool to support computer architecture teaching and learning
B Nova, JC Ferreira, A Araújo
2013 1st International Conference of the Portuguese Society for Engineering …, 2013
342013
A routing protocol for WSN based on the implementation of source routing for minimum cost forwarding method
F Derogarian, JC Ferreira, VG Tavares
Proc. SENSORCOMM, 85, 2011
312011
Parallel implementation of k-means algorithm on fpga
LA Dias, JC Ferreira, MAC Fernandes
IEEE Access 8, 41071-41084, 2020
282020
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices
J Lopes, D Sousa, JC Ferreira
2017 International Conference on ReConFigurable Computing and FPGAs …, 2017
232017
Transparent trace-based binary acceleration for reconfigurable HW/SW systems
J Bispo, N Paulino, JMP Cardoso, JC Ferreira
IEEE Transactions on Industrial Informatics 9 (3), 1625-1634, 2012
222012
Generation of partial FPGA configurations at run-time
ML Silva, JC Ferreira
2008 International Conference on Field Programmable Logic and Applications …, 2008
222008
Improving performance and energy consumption in embedded systems via binary acceleration: A survey
N Paulino, JC Ferreira, JMP Cardoso
ACM Computing Surveys (CSUR) 53 (1), 1-36, 2020
202020
Generation of customized accelerators for loop pipelining of binary instruction traces
NMC Paulino, JC Ferreira, JMP Cardoso
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 21-34, 2016
202016
A wearable sensor network for human locomotion data capture
A Zambrano, F Derogarian, R Dias, MJ Abreu, A Catarino, AM Rocha, ...
pHealth 2012, 216-223, 2012
202012
REFLECT: rendering FPGAs to multi-core embedded computing
JMP Cardoso, PC Diniz, Z Petrov, K Bertels, M Hübner, H van Someren, ...
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, 261-289, 2011
192011
FPGA-based rectification of stereo images
JGP Rodrigues, JC Ferreira
2010 Conference on Design and Architectures for Signal and Image Processing …, 2010
192010
Creation of partial FPGA configurations at run-time
ML Silva, JC Ferreira
2010 13th Euromicro conference on digital system design: Architectures …, 2010
192010
Run-time reconfiguration support for FPGAs with embedded CPUs: The hardware layer
JC Ferreira, MM Silva
19th IEEE International Parallel and Distributed Processing Symposium, 4 pp., 2005
192005
A scalable array for cellular genetic algorithms: TSP as case study
PV dos Santos, JC Alves, JC Ferreira
2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
182012
Optimizing opencl code for performance on fpga: k-means case study with integer data sets
N Paulino, JC Ferreira, JMP Cardoso
IEEE Access 8, 152286-152304, 2020
162020
Dynamically reconfigurable LTE-compliant OFDM modulator for downlink transmission
ML Ferreira, A Barahimi, JC Ferreira
2016 Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2016
162016
The system can't perform the operation now. Try again later.
Articles 1–20