| GKLEE: concolic verification and test generation for GPUs G Li, P Li, G Sawaya, G Gopalakrishnan, I Ghosh, SP Rajan Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of …, 2012 | 188 | 2012 |
| KLOVER: A symbolic execution and automatic test generation tool for C++ programs G Li, I Ghosh, SP Rajan Computer Aided Verification: 23rd International Conference, CAV 2011 …, 2011 | 155 | 2011 |
| SymJS: automatic symbolic testing of JavaScript web applications G Li, E Andreasen, I Ghosh Proceedings of the 22nd ACM SIGSOFT International Symposium on Foundations …, 2014 | 141 | 2014 |
| A fast and low cost testing technique for core-based system-on-chip I Ghosh, S Dey, NK Jha Proceedings of the 35th annual Design Automation Conference, 542-547, 1998 | 128 | 1998 |
| Design for hierarchical testability of RTL circuits obtained by behavioral synthesis I Ghosh, A Raghunathan, NK Jha IEEE transactions on computer-aided design of integrated circuits and …, 1997 | 114 | 1997 |
| Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams I Ghosh, M Fujita IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001 | 107 | 2001 |
| A design-for-testability technique for register-transfer level circuits using control/data flow extraction I Ghosh, A Raghunathan, NK Jha IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998 | 92 | 1998 |
| A low overhead design for testability and test generation technique for core-based systems I Ghosh, NK Jha, S Dey Proceedings International Test Conference 1997, 50-59, 1997 | 80 | 1997 |
| Efficient sequential ATPG for functional RTL circuits L Zhang, I Ghosh, M Hsiao International Test Conference, 2003. Proceedings. ITC 2003., 290-290, 2003 | 78 | 2003 |
| PASS: string solving with parameterized array and interval automaton G Li, I Ghosh Haifa Verification Conference, 15-31, 2013 | 73 | 2013 |
| JST: An automatic test generation tool for industrial Java applications with strings I Ghosh, N Shafiei, G Li, WF Chiang 2013 35th International Conference on Software Engineering (ICSE), 992-1001, 2013 | 67 | 2013 |
| Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits S Bhawmik, I Ghosh, N Jha US Patent 6,463,560, 2002 | 67 | 2002 |
| A design for testability technique for RTL circuits using control/data flow extraction I Ghosh, A Raghunathan, NK Jha Proceedings of International Conference on Computer Aided Design, 329-336, 1996 | 58 | 1996 |
| Using symbolic execution to check global temporal requirements in an application MR Prasad, I Ghosh, SP Rajan US Patent 8,359,576, 2013 | 54 | 2013 |
| Hierarchical test generation and design for testability methods for ASPPs and ASIPs I Ghosh, A Raghunathan, NK Jha IEEE transactions on computer-aided design of integrated circuits and …, 1999 | 53 | 1999 |
| Automatic test pattern generation for functional RTL circuits using assignment decision diagrams I Ghosh, M Fujita Proceedings of the 37th Annual Design Automation Conference, 43-48, 2000 | 52 | 2000 |
| A BIST scheme for RTL circuits based on symbolic testability analysis I Ghosh, NK Jha, S Bhawmik IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000 | 47 | 2000 |
| Generating test sets using intelligent variable selection and test set compaction I Ghosh US Patent 8,479,171, 2013 | 45 | 2013 |
| Symbolic execution and test generation for GPU programs G Li, SP Rajan, I Ghosh US Patent 8,595,701, 2013 | 44 | 2013 |
| A low overhead design for testability and test generation technique for core-based systems-on-a-chip I Ghosh, NK Jha, S Dey IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999 | 44 | 1999 |
Guodong LiNanjing University, University of Utah, Fujitsu Labs of America, Synopsys, GoogleVerified email at cs.utah.edu