| Nano-scale CMOS analog circuits: models and CAD techniques for high-level design S Pandit, C Mandal, A Patra CRC Press, 2018 | 29 | 2018 |
| Smart health monitoring system for temperature, blood oxygen saturation, and heart rate sensing with embedded processing and transmission using IoT platform S Basu, S Saha, S Pandit, S Barman Computational Intelligence in Pattern Recognition: Proceedings of CIPR 2019 …, 2020 | 19 | 2020 |
| Insect moulting hormone, ecdysterone, from Sida carpinifolia Linn. SS Pandit, SD Naik, VS Jathar, AB Kulkarni | 17 | 1976 |
| Modeling and design of a nano scale cmos inverter for symmetric switching characteristics J Mukhopadhyay, S Pandit VLSI Design 2012 (1), 505983, 2012 | 14 | 2012 |
| Systematic methodology for high-level performance modeling of analog systems S Pandit, C Mandal, A Patra 2009 22nd International Conference on VLSI Design, 361-366, 2009 | 13 | 2009 |
| Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET SK Maity, S Pandit International Journal of Electronics 104 (11), 1777-1794, 2017 | 10 | 2017 |
| Study of GS/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model SK Maity, S Pandit Superlattices and Microstructures 101, 362-372, 2017 | 10 | 2017 |
| Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor S Sengupta, S Pandit International Journal of Electronics 102 (6), 967-981, 2015 | 10 | 2015 |
| Channel Profile Design ofDC MOSFET for High Intrinsic Gain and LowMismatch S Sengupta, S Pandit IEEE Transactions on Electron Devices 63 (2), 551-557, 2016 | 9 | 2016 |
| A fast exploration procedure for analog high-level specification translation S Pandit, SK Bhattacharya, C Mandal, A Patra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 8 | 2008 |
| Study of analog and RF performance of UTB-OI-Si substrate MOS transistor using buffered InGaAs and Silicon channel SK Maity, S Pandit 2015 6th International conference on computers and devices for communication …, 2015 | 7 | 2015 |
| Adaptive sampling algorithm for ANN-based performance modeling of nano-scale CMOS inverter D Dhabak, S Pandit World Acad Sci Eng Technol 80, 812-818, 2011 | 6 | 2011 |
| Design of a Nano-scale CMOS Inverter with Symmetric Switching Characteristics using Particle Swarm Optimization Algorithm J Mukhopadhyay, S Pandit IEMCON, 0 | 6* | |
| Study of temperature variation on threshold voltage and sub-threshold slope of EDC MOS transistor including quantum corrections and reduction techniques R Das, AK Gond, S Sengupta, RR Sahani, S Pandit Microsystem Technologies 23 (9), 4221-4229, 2017 | 5 | 2017 |
| Nanoscale MOSFET: MOS transistor as basic building block S Pandit Introduction to Nano: Basics to Nanoscience and Nanotechnology, 145-172, 2015 | 5 | 2015 |
| Analysis of scaling of thickness of the buffer layer on analog/RF and circuit performance of InAs‐OI‐Si MOSFET using NQS model SK Maity, S Pandit International Journal of Numerical Modelling: Electronic Networks, Devices …, 2020 | 4 | 2020 |
| Compact drain current modeling of InAs-OI-Si MOS transistor including quantum confinement SK Maity, S Pandit 2018 International Symposium on Devices, Circuits and Systems (ISDCS), 1-5, 2018 | 4 | 2018 |
| Analysis of Drain Current Local Variability of an n-Channel E DC MOSFET Due to RDD Considering Inversion Charge and Correlated Mobility Fluctuations S Sengupta, S Pandit IEEE Transactions on Electron Devices 65 (4), 1267-1275, 2018 | 4 | 2018 |
| A Methodology for Generation of Performance Models for the Sizing of Analog High‐Level Topologies S Pandit, C Mandal, A Patra VLSI Design 2011 (1), 475952, 2011 | 4 | 2011 |
| An automated high-level topology generation procedure for continuous-time ΣΔ modulator S Pandit, C Mandal, A Patra Integration 43 (3), 289-304, 2010 | 4 | 2010 |
Amit PatraDirector and Professor of Electrical Engineering, IIT (BHU), VaranasiVerified email at ee.iitkgp.ac.in