| Approach to suppress ambipolar conduction in Tunnel FET using dielectric pocket CK Pandey, D Dash, S Chaudhury Micro & Nano Letters 14 (1), 86-90, 2019 | 62 | 2019 |
| A review of tunnel field-effect transistors for improved ON-state behaviour KRN Karthik, CK Pandey Silicon 15 (1), 1-23, 2023 | 48 | 2023 |
| Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances CK Pandey, A Singh, S Chaudhury Applied Physics A 126 (3), 225, 2020 | 46 | 2020 |
| Improvement in analog/RF performances of SOI TFET using dielectric pocket CK Pandey, D Dash, S Chaudhury International Journal of Electronics 107 (11), 1844-1860, 2020 | 40 | 2020 |
| Design and analysis of high k silicon nanotube tunnel FET device A Singh, S Chaudhury, CK Pandey, S Madhulika Sharma, ... IET Circuits, Devices & Systems 13 (8), 1305-1310, 2019 | 39 | 2019 |
| Performance analysis of gate-stack dual-material DG MOSFET using work-function modulation technique for lower technology nodes SK Das, U Nanda, SM Biswal, CK Pandey, LI Giri Silicon 14 (6), 2965-2973, 2022 | 36 | 2022 |
| Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction A Singh, CK Pandey, U Nanda Microelectronics Journal 126, 105512, 2022 | 32 | 2022 |
| Effect of strain in silicon nanotube FET devices for low power applications A Singh, CK Pandey, S Chaudhury, CK Sarkar The European Physical Journal Applied Physics 85 (1), 10101, 2019 | 31 | 2019 |
| Impact of dielectric pocket on analog and high-frequency performances of cylindrical gate-all-around tunnel FETs CK Pandey, D Dash, S Chaudhury ECS Journal of Solid State Science and Technology 7 (5), N59, 2018 | 31 | 2018 |
| Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters KRN Karthik, CK Pandey ECS Journal of Solid State Science and Technology 11 (11), 2022 | 27 | 2022 |
| A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET CK Pandey, A Singh, S Chaudhury Microelectronics Reliability 122, 114166, 2021 | 26 | 2021 |
| Improved DC performances of gate-all-around si-nanotube tunnel FETs using gate-source overlap A Singh, CK Pandey Silicon 14 (4), 1463-1470, 2022 | 24 | 2022 |
| Design and analysis of high performance multiplier circuit I Hussain, CK Pandey, S Chaudhury 2019 Devices for Integrated Circuit (DevIC), 245-247, 2019 | 21 | 2019 |
| Tuning of threshold voltage in silicon nano-tube FET using halo doping and its impact on analog/RF performances A Singh, CK Pandey, S Chaudhury, CK Sarkar Silicon 13 (11), 3871-3877, 2021 | 19 | 2021 |
| Structural, electronic, and mechanical properties of cubic TiO2: A first-principles study D Dash, CK Pandey, S Chaudhury, SK Tripathy Chinese Physics B 27 (1), 017102, 2018 | 19 | 2018 |
| Dual-metal graded-channel double-gate tunnel FETs for reduction of ambipolar conduction CK Pandey, S Chaudhury 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 572-576, 2018 | 18 | 2018 |
| Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET D Das, CK Pandey Microelectronics Reliability 146, 115024, 2023 | 16 | 2023 |
| Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects T Ashok, CK Pandey Physica Scripta 99 (2), 025005, 2024 | 13 | 2024 |
| Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET AK Pathakamuri, CK Pandey Physica Scripta 98 (12), 124001, 2023 | 13 | 2023 |
| A Dual-Drain Vertical Tunnel FET with Improved Device Performance: Proposal, Optimization, and Investigation D Das, CK Pandey ECS Journal of Solid State Science and Technology, 2022 | 12 | 2022 |
Saurabh ChaudhuryProfessor, NIT SilcharVerified email at nits.ac.in