Vassilis Papaefstathiou

Cited by

	All	Since 2020
Citations	785	373
h-index	15	11
i10-index	23	16

200620072008200920102011201220132014201520162017201820192020202120222023202420257 12 7 14 32 22 8 22 34 37 36 44 55 59 71 61 71 89 76 5

Public access

View all

24 articles

7 articles

available

not available

Based on funding mandates

Co-authors

Manolis G.H. KatevenisFORTH-ICS (ics.forth.gr) and Computer Science Department, University of Crete (csd.uoc.gr)Verified email at ics.forth.gr
Dionisios PnevmatikatosProfessor of ECE, National Technical University of AthensVerified email at cslab.ece.ntua.gr
Ioannis SourdisProfessor of Computer Engineering, Chalmers University of TechnologyVerified email at chalmers.se
Stamatis Kavvadias(no current affiliation)Verified email at csd.uoc.gr
Ioannis PapaefstathiouProfessor, School of ECE, Aristotle University of ThessalonikiVerified email at ece.auth.gr
Manolis MarazakisStaff Research Scientist, FORTH-ICSVerified email at ics.forth.gr
Nikolaos ChrysosFoundation For Research & Technology (FORTH) -- HellasVerified email at ics.forth.gr
Pedro TrancosoDepartment of Computer Science and Engineering, Chalmers University of TechnologyVerified email at chalmers.se
Per StenströmChalmers University of TechnologyVerified email at chalmers.se
Miquel PericàsChalmers University of TechnologyVerified email at chalmers.se
Sotiris IoannidisTechnical University of Crete and Foundation for Research and Technology - HellasVerified email at ece.tuc.gr
Angelos BilasProfessor of Computer Science, University of Crete & FORTH, GreeceVerified email at csd.uoc.gr
Dirk KochSchool of Computer Science, University of ManchesterVerified email at recobus.de
Luciano LavagnoPolitecnico di TorinoVerified email at polito.it
John GoodacreProfessor Computer Architectures, School of Computer Science, University of ManchesterVerified email at manchester.ac.uk
Christoforos KachrisUniversity of West AtticaVerified email at uniwa.gr
George MichelogiannakisLawrence Berkeley National LaboratoryVerified email at lbl.gov
Federico SillaFull Professor at Universitat Politecnica de Valencia, SpainVerified email at disca.upv.es
Pranav TendulkarPhD Candidate, Verimag, University of GrenobleVerified email at imag.fr
Carlos VillaviejaGoogleVerified email at google.com

Vassilis Papaefstathiou

Computer Science Department, University of Crete and FORTH-ICS

Verified email at csd.uoc.gr - Homepage

Computer Architecture High-Performance Computing FPGA Prototyping


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
ASIST: architectural support for instruction set randomization A Papadogiannakis, L Loutsis, V Papaefstathiou, S Ioannidis Proceedings of the 2013 ACM SIGSAC conference on Computer & communications …, 2013	73	2013
Memory-efficient 5D packet classification at 40 Gbps I Papaefstathiou, V Papaefstathiou IEEE INFOCOM 2007-26th IEEE International Conference on Computer …, 2007	57	2007
Ecoscale: Reconfigurable computing and runtime system for future exascale systems I Mavroidis, I Papaefstathiou, L Lavagno, DS Nikolopoulos, D Koch, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 696-701, 2016	56	2016
Prefetching and cache management using task lifetimes V Papaefstathiou, MGH Katevenis, DS Nikolopoulos, D Pnevmatikatos Proceedings of the 27th international ACM conference on International …, 2013	51	2013
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G Kalokerinos, V Papaefstathiou, G Nikiforos, S Kavadias, M Katevenis, ... 2009 International Symposium on Systems, Architectures, Modeling, and …, 2009	40	2009
Hybrid2: Combining caching and migration in hybrid memory systems E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020	34	2020
Formic: Cost-efficient and scalable prototyping of manycore architectures S Lyberis, G Kalokerinos, M Lygerakis, V Papaefstathiou, D Tsaliagkos, ... 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012	32	2012
RADAR: Runtime-assisted dead region management for last-level caches M Manivannan, V Papaefstathiou, M Pericas, P Stenstrom 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016	29	2016
Modeling energy-performance tradeoffs in ARM big. LITTLE architectures E Vasilakis, I Sourdis, V Papaefstathiou, A Psathakis, MGH Katevenis 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017	22	2017
LLC-guided data migration in hybrid memory systems E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis 2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019	20	2019
Decoupled fused cache: Fusing a decoupled LLC with a DRAM cache E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis ACM Transactions on Architecture and Code Optimization (TACO) 15 (4), 1-23, 2019	19	2019
A systematic evaluation of emerging mesh-like cmp nocs A Psathakis, V Papaefstathiou, N Chrysos, F Chaix, E Vasilakis, ... 2015 ACM/IEEE Symposium on Architectures for Networking and Communications …, 2015	18	2015
Efficient Remote Block-level I/O over an RDMA-capable NIC M Marazakis, K Xinidis, V Papaefstathiou, A Bilas Proceedings of the 20th annual international conference on Supercomputing …, 2006	17	2006
Explicit communication and synchronization in SARC M Katevenis, V Papaefstathiou, S Kavadias, D Pnevmatikatos, F Silla, ... IEEE micro 30 (5), 30-41, 2010	16	2010
DDRNoC: Dual Data-Rate Network-on-Chip A Ejaz, V Papaefstathiou, I Sourdis ACM Transactions on Architecture and Code Optimization (TACO) 15 (2), 25, 2018	15	2018
Odd-ecc: on-demand dram error correcting codes A Malek, E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis Proceedings of the International Symposium on Memory Systems, 96-111, 2017	15	2017
Multilevel simulation-based co-design of next generation HPC microprocessors L Zaourar, M Benazouz, A Mouhagir, F Jebali, T Sassolas, JC Weill, ... 2021 International Workshop on Performance Modeling, Benchmarking and …, 2021	14	2021
FreewayNoC: A DDR NoC with pipeline bypassing A Ejaz, V Papaefstathiou, I Sourdis 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018	13	2018
SLOOP: QoS-supervised loop execution to reduce energy on heterogeneous architectures MW Azhar, P Stenström, V Papaefstathiou ACM Transactions on Architecture and Code Optimization (TACO) 14 (4), 1-25, 2017	13	2017
Implementation and impact of an ultra-compact multi-FPGA board for large system prototyping F Chaix, A Ioannou, N Kossifidis, N Dimou, G Ieronymakis, M Marazakis, ... 2019 IEEE/ACM International Workshop on Heterogeneous High-performance …, 2019	12	2019

The system can't perform the operation now. Try again later.

Articles 1–20

Citations per year

Duplicate citations

Merged citations

Add co-authorsCo-authors

Follow

Cited by

Co-authors