| Low latency YOLOv3-tiny accelerator for low-cost FPGA using general matrix multiplication principle T Adiono, A Putra, N Sutisna, I Syafalni, R Mulyawan IEEE access 9, 141890-141913, 2021 | 39 | 2021 |
| Efficient homomorphic encryption accelerator with integrated PRNG using low-cost FPGA I Syafalni, G Jonatan, N Sutisna, R Mulyawan, T Adiono IEEE Access 10, 7753-7771, 2022 | 37 | 2022 |
| Conceptual review on number theoretic transform and comprehensive review on its implementations A Satriawan, I Syafalni, R Mareta, I Anshori, W Shalannanda, A Barra IEEE Access, 2023 | 27 | 2023 |
| Quantum-enhanced support vector machine for sentiment classification FZ Ruskanda, MR Abiwardani, R Mulyawan, I Syafalni, HT Larasati IEEE Access 11, 87520-87532, 2023 | 15 | 2023 |
| Farane-q: Fast parallel and pipeline q-learning accelerator for configurable reinforcement learning soc N Sutisna, AMR Ilmy, I Syafalni, R Mulyawan, T Adiono IEEE Access 11, 144-161, 2022 | 15 | 2022 |
| Soft-error tolerant TCAMs for high-reliability packet classifications I Syafalni, T Sasao, X Wen, S Holst, K Miyase 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 471-474, 2014 | 15 | 2014 |
| A method to detect bit flips in a soft-error resilient TCAM I Syafalni, T Sasao, X Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 10 | 2017 |
| Comparison of MPPT based on Deep Reinforcement Learning by DQN, DDPG and TD3 J Panggabean, N Sutisna, I Syafalni, T Adiono 2023 Asia Pacific Signal and Information Processing Association Annual …, 2023 | 8 | 2023 |
| Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture T Adiono, RM Ramadhan, N Sutisna, I Syafalni, R Mulyawan, CH Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 8 | 2023 |
| Assertion-based verification of industrial WLAN system I Syafalni, N Surantha, DK Lam, N Sutisna, Y Nagao, K Wakasugi, ... 2016 IEEE international symposium on circuits and systems (ISCAS), 982-985, 2016 | 8 | 2016 |
| Simple sentiment analysis ansatz for sentiment classification in quantum natural language processing FZ Ruskanda, MR Abiwardani, I Syafalni, HT Larasati, R Mulyawan IEEE Access 11, 120612-120627, 2023 | 7 | 2023 |
| Polynomial multiplication systolic array for homomorphic encryption in secure network communications N Sutisna, G Jonatan, I Syafalni, R Mulyawan, T Adiono 2020 IEEE International Conference on Communication, Networks and Satellite …, 2020 | 7 | 2020 |
| Head-tail expressions for interval functions I Syafalni, T Sasao IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2014 | 7 | 2014 |
| A TCAM generator for packet classification I Syafalni, T Sasao 2013 IEEE 31st International Conference on Computer Design (ICCD), 322-328, 2013 | 7 | 2013 |
| On the numbers of products in prefix SOPs for interval functions I Syafalni, T Sasao IEICE TRANSACTIONS on Information and Systems 96 (5), 1086-1094, 2013 | 7 | 2013 |
| Head-Tail Expressions for Interval Functions I Syafalni, T Sasao The 17th Workshop on Synthesis And System Integration of Mixed Information …, 2012 | 7 | 2012 |
| Quantum representation for sentiment classification FZ Ruskanda, MR Abiwardani, MA Al Bari, KA Bagaspati, R Mulyawan, ... 2022 IEEE International Conference on Quantum Computing and Engineering (QCE …, 2022 | 6 | 2022 |
| Digit-number speech-recognition using spectrogram-based convolutional neural network C Amadeus, I Syafalni, N Sutisna, T Adiono 2022 International Symposium on Electronics and Smart Devices (ISESD), 1-6, 2022 | 5 | 2022 |
| Dynamic pilot allocation for channel estimation in high-mobility OFDM receiver R Mulyawan, R Averly, I Syafalni, N Sutisna, T Adiono 2021 International Conference on Electronics, Information, and Communication …, 2021 | 5 | 2021 |
| Cloud security implementation using homomorphic encryption I Syafalni, H Fadhli, W Utami, GSA Dharma, R Mulyawan, N Sutisna, ... 2020 IEEE International Conference on Communication, Networks and Satellite …, 2020 | 5 | 2020 |
Trio AdionoProfessor in Chip Design, STEI, Institut Teknologi BandungVerified email at stei.itb.ac.id