| High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier J Tian, B Wu, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers, 2021 | 33 | 2021 |
| AC-PM: An area-efficient and configurable polynomial multiplier for lattice based cryptography X Hu, J Tian, M Li, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers 70 (2), 719-732, 2022 | 29 | 2022 |
| Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber M Li, J Tian, X Hu, Z Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 24 | 2023 |
| Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography J Tian, J Lin, Z Wang 2019 IEEE International Workshop on Signal Processing Systems (SiPS), 2019 | 18 | 2019 |
| A 21.66 Gbps nonbinary LDPC decoder for high-speed communications J Tian, J Lin, Z Wang IEEE Transactions on Circuits and Systems II: Express Briefs 65 (2), 226-230, 2017 | 16 | 2017 |
| Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography J Tian, J Lin, Z Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020 | 14 | 2020 |
| Optimized trellis-based min-max decoder for NB-LDPC codes J Tian, S Song, J Lin, Z Wang IEEE Transactions on Circuits and Systems II: Express Briefs 67 (1), 57-61, 2019 | 14 | 2019 |
| Efficient software implementation of the SIKE protocol using a new data representation J Tian, P Wang, Z Liu, J Lin, Z Wang, J Großschädl IEEE Transactions on Computers 71 (3), 670-683, 2021 | 13 | 2021 |
| High-speed and scalable FPGA implementation of the key generation for the Leighton-Micali signature protocol Y Song, X Hu, W Wang, J Tian, Z Wang 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 11 | 2021 |
| An efficient accelerator of the squaring for the verifiable delay function over a class group D Zhu, Y Song, J Tian, Z Wang, H Yu 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 137-140, 2020 | 11 | 2020 |
| Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders W Li, J Tian, J Lin, Z Wang IEEE Communications Letters, 2019 | 9 | 2019 |
| Efficient T-EMS Based Algorithms for High-Order LDPC Codes J Tian, S Song, J Lin, Z Wang IEEE Access, 2019 | 9 | 2019 |
| Low-latency architecture for the parallel extended GCD algorithm of large numbers D Zhu, J Tian, Z Wang 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 7 | 2021 |
| A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography B Wu, J Tian, X Hu, Z Wang 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020 | 7 | 2020 |
| A novel iterative reliability-based majority-logic decoder for NB-LDPC codes S Song, H Cui, J Tian, J Lin, Z Wang IEEE Transactions on Circuits and Systems II: Express Briefs 67 (8), 1399-1403, 2019 | 7 | 2019 |
| High-throughput hardware implementation for haraka in sphincs+ Y Dai, Y Song, J Tian, Z Wang 2023 24th International Symposium on Quality Electronic Design (ISQED), 1-6, 2023 | 6 | 2023 |
| Efficient homomorphic convolution designs on FPGA for secure inference X Hu, M Li, J Tian, Z Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (11 …, 2022 | 6 | 2022 |
| Fast permutation architecture on encrypted data for secure neural network inference X Hu, J Tian, Z Wang 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 141-144, 2020 | 6 | 2020 |
| DARM: A low-complexity and fast modular multiplier for lattice-based cryptography X Hu, M Li, J Tian, Z Wang 2021 IEEE 32nd International Conference on Application-specific Systems …, 2021 | 5 | 2021 |
| High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber M Li, J Tian, X Hu, Y Cao, Z Wang 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 1-5, 2022 | 4 | 2022 |
Zhongfeng WangNanjing UniversityVerified email at nju.edu.cn